Lines Matching +full:pwm +full:- +full:names
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3568-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/rk3568-power.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
57 #address-cells = <2>;
58 #size-cells = <0>;
62 compatible = "arm,cortex-a55";
64 enable-method = "psci";
66 operating-points-v2 = <&cpu0_opp_table>;
71 compatible = "arm,cortex-a55";
73 enable-method = "psci";
75 operating-points-v2 = <&cpu0_opp_table>;
80 compatible = "arm,cortex-a55";
82 enable-method = "psci";
84 operating-points-v2 = <&cpu0_opp_table>;
89 compatible = "arm,cortex-a55";
91 enable-method = "psci";
93 operating-points-v2 = <&cpu0_opp_table>;
97 cpu0_opp_table: cpu0-opp-table {
98 compatible = "operating-points-v2";
99 opp-shared;
101 opp-408000000 {
102 opp-hz = /bits/ 64 <408000000>;
103 opp-microvolt = <1000000 1000000 1250000>;
104 clock-latency-ns = <40000>;
106 opp-600000000 {
107 opp-hz = /bits/ 64 <600000000>;
108 opp-microvolt = <1000000 1000000 1250000>;
109 clock-latency-ns = <40000>;
111 opp-816000000 {
112 opp-hz = /bits/ 64 <816000000>;
113 opp-microvolt = <1000000 1000000 1250000>;
114 clock-latency-ns = <40000>;
115 opp-suspend;
117 opp-1008000000 {
118 opp-hz = /bits/ 64 <1008000000>;
119 opp-microvolt = <1000000 1000000 1250000>;
120 clock-latency-ns = <40000>;
122 opp-1200000000 {
123 opp-hz = /bits/ 64 <1200000000>;
124 opp-microvolt = <1000000 1000000 1250000>;
125 clock-latency-ns = <40000>;
129 arm-pmu {
130 compatible = "arm,cortex-a55-pmu", "arm,armv8-pmuv3";
135 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
138 display_subsystem: display-subsystem {
139 compatible = "rockchip,display-subsystem";
143 mpp_srv: mpp-srv {
144 compatible = "rockchip,mpp-service";
145 rockchip,taskqueue-count = <5>;
146 rockchip,resetgroup-count = <5>;
151 compatible = "arm,psci-1.0";
155 thermal_zones: thermal-zones {
156 soc_thermal: soc-thermal {
157 polling-delay-passive = <20>; /* milliseconds */
158 polling-delay = <1000>; /* milliseconds */
160 thermal-sensors = <&tsadc 0>;
162 soc_crit: soc-crit {
172 gpu_thermal: gpu-thermal {
173 polling-delay-passive = <20>; /* milliseconds */
174 polling-delay = <1000>; /* milliseconds */
176 thermal-sensors = <&tsadc 1>;
181 compatible = "arm,armv8-timer";
188 gmac0_clkin: external-gmac0-clock {
189 compatible = "fixed-clock";
190 clock-frequency = <125000000>;
191 clock-output-names = "gmac0_clkin";
192 #clock-cells = <0>;
195 gmac1_clkin: external-gmac1-clock {
196 compatible = "fixed-clock";
197 clock-frequency = <125000000>;
198 clock-output-names = "gmac1_clkin";
199 #clock-cells = <0>;
203 compatible = "fixed-clock";
204 #clock-cells = <0>;
205 clock-frequency = <24000000>;
206 clock-output-names = "xin24m";
210 compatible = "snps,dwc-ahci";
214 clock-names = "sata", "pmalive", "rxoob";
216 interrupt-names = "hostc";
218 phy-names = "sata-phy";
219 ports-implemented = <0x1>;
220 power-domains = <&power RK3568_PD_PIPE>;
225 compatible = "snps,dwc-ahci";
229 clock-names = "sata", "pmalive", "rxoob";
231 interrupt-names = "hostc";
233 phy-names = "sata-phy";
234 ports-implemented = <0x1>;
235 power-domains = <&power RK3568_PD_PIPE>;
240 compatible = "snps,dwc-ahci";
244 clock-names = "sata", "pmalive", "rxoob";
246 interrupt-names = "hostc";
248 phy-names = "sata-phy";
249 ports-implemented = <0x1>;
250 power-domains = <&power RK3568_PD_PIPE>;
255 compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3";
258 clock-names = "ref_clk", "suspend_clk",
260 #address-cells = <2>;
261 #size-cells = <2>;
271 phy-names = "usb2-phy";
273 power-domains = <&power RK3568_PD_PIPE>;
275 reset-names = "usb3-otg";
277 snps,dis-u2-freeclk-exists-quirk;
279 snps,dis-del-phy-power-chg-quirk;
280 snps,dis-tx-ipgap-linecheck-quirk;
281 snps,xhci-trb-ent-quirk;
287 compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3";
290 clock-names = "ref_clk", "suspend_clk",
292 #address-cells = <2>;
293 #size-cells = <2>;
303 phy-names = "usb2-phy";
305 power-domains = <&power RK3568_PD_PIPE>;
307 reset-names = "usb3-host";
309 snps,dis-u2-freeclk-exists-quirk;
311 snps,dis-del-phy-power-chg-quirk;
312 snps,dis-tx-ipgap-linecheck-quirk;
313 snps,xhci-trb-ent-quirk;
318 gic: interrupt-controller@fd400000 {
319 compatible = "arm,gic-v3";
320 #interrupt-cells = <3>;
321 #address-cells = <2>;
322 #size-cells = <2>;
324 interrupt-controller;
329 its: interrupt-controller@fd440000 {
330 compatible = "arm,gic-v3-its";
331 msi-controller;
338 compatible = "generic-ehci";
343 clock-names = "usbhost", "arbiter", "pclk", "utmi";
345 phy-names = "usb2-phy";
350 compatible = "generic-ohci";
355 clock-names = "usbhost", "arbiter", "pclk", "utmi";
357 phy-names = "usb2-phy";
362 compatible = "generic-ehci";
367 clock-names = "usbhost", "arbiter", "pclk", "utmi";
369 phy-names = "usb2-phy";
374 compatible = "generic-ohci";
379 clock-names = "usbhost", "arbiter", "pclk", "utmi";
381 phy-names = "usb2-phy";
386 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
389 pmu_io_domains: io-domains {
390 compatible = "rockchip,rk3568-pmu-io-voltage-domain";
394 reboot_mode: reboot-mode {
395 compatible = "syscon-reboot-mode";
397 mode-bootloader = <BOOT_BL_DOWNLOAD>;
398 mode-charge = <BOOT_CHARGING>;
399 mode-fastboot = <BOOT_FASTBOOT>;
400 mode-loader = <BOOT_BL_DOWNLOAD>;
401 mode-normal = <BOOT_NORMAL>;
402 mode-recovery = <BOOT_RECOVERY>;
403 mode-ums = <BOOT_UMS>;
404 mode-panic = <BOOT_PANIC>;
405 mode-watchdog = <BOOT_WATCHDOG>;
410 compatible = "rockchip,rk3568-pipegrf", "syscon";
415 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
418 io_domains: io-domains {
419 compatible = "rockchip,rk3568-io-voltage-domain";
424 compatible = "rockchip,rk3568-lvds";
426 phy-names = "phy";
430 #address-cells = <1>;
431 #size-cells = <0>;
435 #address-cells = <1>;
436 #size-cells = <0>;
440 remote-endpoint = <&vp1_out_lvds0>;
445 remote-endpoint = <&vp2_out_lvds0>;
452 compatible = "rockchip,rk3568-lvds";
454 phy-names = "phy";
458 #address-cells = <1>;
459 #size-cells = <0>;
463 #address-cells = <1>;
464 #size-cells = <0>;
468 remote-endpoint = <&vp1_out_lvds1>;
473 remote-endpoint = <&vp2_out_lvds1>;
480 compatible = "rockchip,rk3568-rgb";
481 pinctrl-names = "default";
482 pinctrl-0 = <&lcdc_ctl>;
486 #address-cells = <1>;
487 #size-cells = <0>;
491 #address-cells = <1>;
492 #size-cells = <0>;
496 remote-endpoint = <&vp2_out_rgb>;
506 compatible = "rockchip,pipe-phy-grf", "syscon";
511 compatible = "rockchip,pipe-phy-grf", "syscon";
516 compatible = "rockchip,pipe-phy-grf", "syscon";
521 compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
526 compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
530 edp_phy: edp-phy@fdcb0000 {
531 compatible = "rockchip,rk3568-edp-phy";
534 clock-names = "refclk", "pclk";
536 reset-names = "apb";
537 #phy-cells = <0>;
542 compatible = "rockchip,pcie30-phy-grf", "syscon";
546 pmucru: clock-controller@fdd00000 {
547 compatible = "rockchip,rk3568-pmucru";
550 #clock-cells = <1>;
551 #reset-cells = <1>;
554 cru: clock-controller@fdd20000 {
555 compatible = "rockchip,rk3568-cru";
558 #clock-cells = <1>;
559 #reset-cells = <1>;
561 assigned-clocks =
570 assigned-clock-rates =
579 assigned-clock-parents =
584 compatible = "rockchip,rk3399-i2c";
587 clock-names = "i2c", "pclk";
589 pinctrl-names = "default";
590 pinctrl-0 = <&i2c0_xfer>;
591 #address-cells = <1>;
592 #size-cells = <0>;
597 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
601 clock-names = "baudclk", "apb_pclk";
602 reg-shift = <2>;
603 reg-io-width = <4>;
605 pinctrl-names = "default";
606 pinctrl-0 = <&uart0_xfer>;
610 pwm0: pwm@fdd70000 {
611 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
613 #pwm-cells = <3>;
614 pinctrl-names = "active";
615 pinctrl-0 = <&pwm0m0_pins>;
617 clock-names = "pwm", "pclk";
621 pwm1: pwm@fdd70010 {
622 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
624 #pwm-cells = <3>;
625 pinctrl-names = "active";
626 pinctrl-0 = <&pwm1m0_pins>;
628 clock-names = "pwm", "pclk";
632 pwm2: pwm@fdd70020 {
633 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
635 #pwm-cells = <3>;
636 pinctrl-names = "active";
637 pinctrl-0 = <&pwm2m0_pins>;
639 clock-names = "pwm", "pclk";
643 pwm3: pwm@fdd70030 {
644 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
646 #pwm-cells = <3>;
647 pinctrl-names = "active";
648 pinctrl-0 = <&pwm3_pins>;
650 clock-names = "pwm", "pclk";
654 pmu: power-management@fdd90000 {
655 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
658 power: power-controller {
659 compatible = "rockchip,rk3568-power-controller";
660 #power-domain-cells = <1>;
661 #address-cells = <1>;
662 #size-cells = <0>;
742 compatible = "rockchip,rk3568-core-pvtm";
744 #address-cells = <1>;
745 #size-cells = <0>;
749 clock-names = "clk", "pclk";
751 reset-names = "rts", "rst-p";
752 thermal-zone = "soc-thermal";
757 compatible = "arm,malit602", "arm,malit60x", "arm,malit6xx", "arm,mali-midgard";
763 interrupt-names = "GPU", "MMU", "JOB";
769 clock-names = "clk_mali";
770 power-domains = <&power RK3568_PD_GPU>;
771 #cooling-cells = <2>;
772 operating-points-v2 = <&gpu_opp_table>;
776 compatible = "arm,mali-simple-power-model";
777 static-coefficient = <411000>;
778 dynamic-coefficient = <733>;
779 ts = <32000 4700 (-80) 2>;
780 thermal-zone = "gpu-thermal";
784 gpu_opp_table: opp-table2 {
785 compatible = "operating-points-v2";
787 opp-200000000 {
788 opp-hz = /bits/ 64 <200000000>;
789 opp-microvolt = <1000000>;
791 opp-300000000 {
792 opp-hz = /bits/ 64 <300000000>;
793 opp-microvolt = <1000000>;
795 opp-400000000 {
796 opp-hz = /bits/ 64 <400000000>;
797 opp-microvolt = <1000000>;
799 opp-600000000 {
800 opp-hz = /bits/ 64 <600000000>;
801 opp-microvolt = <1000000>;
806 compatible = "rockchip,rk3568-gpu-pvtm";
808 #address-cells = <1>;
809 #size-cells = <0>;
813 clock-names = "clk", "pclk";
815 reset-names = "rts", "rst-p";
816 thermal-zone = "gpu-thermal";
821 compatible = "rockchip,rk3568-npu-pvtm";
823 #address-cells = <1>;
824 #size-cells = <0>;
829 clock-names = "clk", "pclk", "hclk";
831 reset-names = "rts", "rst-p";
832 thermal-zone = "soc-thermal";
837 compatible = "rockchip,vpu-decoder-v2";
840 interrupt-names = "irq_dec";
842 clock-names = "aclk_vcodec", "hclk_vcodec";
844 reset-names = "video_a", "video_h";
846 power-domains = <&power RK3568_PD_VPU>;
848 rockchip,taskqueue-node = <0>;
849 rockchip,resetgroup-node = <0>;
854 compatible = "rockchip,iommu-v2";
857 interrupt-names = "vdpu_mmu";
858 clock-names = "aclk", "iface";
860 power-domains = <&power RK3568_PD_VPU>;
861 #iommu-cells = <0>;
870 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
871 power-domains = <&power RK3568_PD_RGA>;
876 compatible = "rockchip,rk3568-ebc-tcon";
880 clock-names = "hclk", "dclk";
881 power-domains = <&power RK3568_PD_RGA>;
883 pinctrl-names = "default";
884 pinctrl-0 = <&ebc_pins>;
889 compatible = "rockchip,rkv-jpeg-decoder-v1";
893 clock-names = "aclk_vcodec", "hclk_vcodec";
894 rockchip,normal-rates = <297000000>, <0>;
896 reset-names = "video_a", "video_h";
899 rockchip,taskqueue-node = <1>;
900 rockchip,resetgroup-node = <1>;
901 power-domains = <&power RK3568_PD_RGA>;
906 compatible = "rockchip,iommu-v2";
909 interrupt-names = "jpegd_mmu";
910 clock-names = "aclk", "iface";
912 power-domains = <&power RK3568_PD_RGA>;
913 #iommu-cells = <0>;
918 compatible = "rockchip,vpu-encoder-v2";
922 clock-names = "aclk_vcodec", "hclk_vcodec";
923 rockchip,normal-rates = <297000000>, <0>;
925 reset-names = "video_a", "video_h";
928 rockchip,taskqueue-node = <2>;
929 rockchip,resetgroup-node = <2>;
930 power-domains = <&power RK3568_PD_RGA>;
935 compatible = "rockchip,iommu-v2";
938 interrupt-names = "vepu_mmu";
939 clock-names = "aclk", "iface";
941 power-domains = <&power RK3568_PD_RGA>;
942 #iommu-cells = <0>;
947 compatible = "rockchip,iep-v2";
951 clock-names = "aclk", "hclk", "sclk";
954 reset-names = "rst_a", "rst_h", "rst_s";
955 power-domains = <&power RK3568_PD_RGA>;
957 rockchip,taskqueue-node = <5>;
958 rockchip,resetgroup-node = <5>;
964 compatible = "rockchip,iommu-v2";
967 interrupt-names = "iep_mmu";
969 clock-names = "aclk", "iface";
970 #iommu-cells = <0>;
971 power-domains = <&power RK3568_PD_RGA>;
972 //rockchip,disable-device-link-resume;
977 compatible = "rockchip,rk3568-eink-tcon";
981 clock-names = "pclk", "hclk";
986 compatible = "rockchip,rkv-encoder-v1";
989 interrupt-names = "irq_enc";
992 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
993 rockchip,normal-rates = <297000000>, <0>, <400000000>;
994 rockchip,advanced-rates = <297000000>, <0>, <500000000>;
995 rockchip,default-max-load = <2088960>;
998 reset-names = "video_a", "video_h", "video_core";
999 assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_RKVENC_CORE>;
1000 assigned-clock-rates = <297000000>, <297000000>;
1002 node-name = "rkvenc";
1004 rockchip,taskqueue-node = <3>;
1005 rockchip,resetgroup-node = <3>;
1006 power-domains = <&power RK3568_PD_RKVENC>;
1011 compatible = "rockchip,iommu-v2";
1015 interrupt-names = "rkvenc_mmu0", "rkvenc_mmu1";
1017 clock-names = "aclk", "iface";
1018 rockchip,disable-mmu-reset;
1019 rockchip,enable-cmd-retry;
1020 #iommu-cells = <0>;
1021 power-domains = <&power RK3568_PD_RKVENC>;
1026 compatible = "rockchip,rkv-decoder-v2";
1029 interrupt-names = "irq_dec";
1033 clock-names = "aclk_vcodec", "hclk_vcodec","clk_cabac",
1035 rockchip,normal-rates = <297000000>, <0>, <297000000>,
1037 rockchip,advanced-rates = <400000000>, <0>, <400000000>,
1039 rockchip,default-max-load = <2088960>;
1043 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_RKVDEC_CA>,
1045 assigned-clock-rates = <297000000>, <297000000>, <297000000>, <297000000>;
1046 reset-names = "video_a", "video_h", "video_cabac",
1048 power-domains = <&power RK3568_PD_RKVDEC>;
1051 rockchip,taskqueue-node = <4>;
1052 rockchip,resetgroup-node = <4>;
1057 compatible = "rockchip,iommu-v2";
1060 interrupt-names = "rkvdec_mmu";
1062 clock-names = "aclk", "iface";
1063 power-domains = <&power RK3568_PD_RKVDEC>;
1064 #iommu-cells = <0>;
1068 mipi_csi2: mipi-csi2@fdfb0000 {
1069 compatible = "rockchip,rk3568-mipi-csi2";
1071 reg-names = "csihost_regs";
1074 interrupt-names = "csi-intr1", "csi-intr2";
1076 clock-names = "pclk_csi2host", "srst_csihost_p";
1077 power-domains = <&power RK3568_PD_VI>;
1082 compatible = "rockchip,rk3568-cif";
1084 reg-names = "cif_regs";
1086 interrupt-names = "cif-intr";
1090 clock-names = "aclk_cif", "hclk_cif",
1095 reset-names = "rst_cif_a", "rst_cif_h",
1098 assigned-clocks = <&cru DCLK_VICAP>;
1099 assigned-clock-rates = <300000000>;
1100 power-domains = <&power RK3568_PD_VI>;
1110 interrupt-names = "cif_mmu";
1112 clock-names = "aclk", "iface";
1113 power-domains = <&power RK3568_PD_VI>;
1114 #iommu-cells = <0>;
1115 rockchip,disable-mmu-reset;
1120 compatible = "rockchip,rkcif-dvp";
1127 compatible = "rockchip,rkcif-sditf";
1133 compatible = "rockchip,rkcif-mipi-lvds";
1140 compatible = "rockchip,rkcif-sditf";
1146 compatible = "rockchip,rk3568-rkisp";
1151 interrupt-names = "mipi_irq", "mi_irq", "isp_irq";
1153 clock-names = "aclk_isp", "hclk_isp", "clk_isp";
1155 reset-names = "isp", "isp-h";
1157 power-domains = <&power RK3568_PD_VI>;
1166 interrupt-names = "isp_mmu";
1168 clock-names = "aclk", "iface";
1169 power-domains = <&power RK3568_PD_VI>;
1170 #iommu-cells = <0>;
1171 rockchip,disable-mmu-reset;
1175 rkisp_vir0: rkisp-vir0 {
1176 compatible = "rockchip,rkisp-vir";
1181 rkisp_vir1: rkisp-vir1 {
1182 compatible = "rockchip,rkisp-vir";
1188 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
1192 interrupt-names = "macirq", "eth_wake_irq";
1198 clock-names = "stmmaceth", "mac_clk_rx",
1203 reset-names = "stmmaceth";
1205 snps,mixed-burst;
1208 snps,axi-config = <&gmac1_stmmac_axi_setup>;
1209 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
1210 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
1214 compatible = "snps,dwmac-mdio";
1215 #address-cells = <0x1>;
1216 #size-cells = <0x0>;
1219 gmac1_stmmac_axi_setup: stmmac-axi-config {
1225 gmac1_mtl_rx_setup: rx-queues-config {
1226 snps,rx-queues-to-use = <1>;
1230 gmac1_mtl_tx_setup: tx-queues-config {
1231 snps,tx-queues-to-use = <1>;
1237 compatible = "rockchip,rk3568-vop";
1239 reg-names = "regs";
1243 clock-names = "aclk_vop", "hclk_vop", "dclk_vp0", "dclk_vp1", "dclk_vp2";
1245 power-domains = <&power RK3568_PD_VO>;
1249 #address-cells = <1>;
1250 #size-cells = <0>;
1253 #address-cells = <1>;
1254 #size-cells = <0>;
1259 remote-endpoint = <&dsi0_in_vp0>;
1264 remote-endpoint = <&dsi1_in_vp0>;
1269 remote-endpoint = <&edp_in_vp0>;
1274 remote-endpoint = <&hdmi_in_vp0>;
1279 #address-cells = <1>;
1280 #size-cells = <0>;
1285 remote-endpoint = <&dsi0_in_vp1>;
1290 remote-endpoint = <&dsi1_in_vp1>;
1295 remote-endpoint = <&edp_in_vp1>;
1300 remote-endpoint = <&hdmi_in_vp1>;
1305 remote-endpoint = <&lvds0_in_vp1>;
1310 remote-endpoint = <&lvds1_in_vp1>;
1316 #address-cells = <1>;
1317 #size-cells = <0>;
1323 remote-endpoint = <&lvds0_in_vp2>;
1328 remote-endpoint = <&lvds1_in_vp2>;
1333 remote-endpoint = <&rgb_in_vp2>;
1340 compatible = "rockchip,iommu-v2";
1343 interrupt-names = "vop_mmu";
1345 clock-names = "aclk", "iface";
1346 #iommu-cells = <0>;
1351 compatible = "rockchip,rk3568-mipi-dsi";
1355 clock-names = "pclk", "hclk", "hs_clk";
1357 reset-names = "apb";
1359 phy-names = "mipi_dphy";
1360 power-domains = <&power RK3568_PD_VO>;
1362 #address-cells = <1>;
1363 #size-cells = <0>;
1367 #address-cells = <1>;
1368 #size-cells = <0>;
1372 #address-cells = <1>;
1373 #size-cells = <0>;
1377 remote-endpoint = <&vp0_out_dsi0>;
1382 remote-endpoint = <&vp1_out_dsi0>;
1389 compatible = "rockchip,rk3568-mipi-dsi";
1393 clock-names = "pclk", "hclk", "hs_clk";
1395 reset-names = "apb";
1397 phy-names = "mipi_dphy";
1398 power-domains = <&power RK3568_PD_VO>;
1400 #address-cells = <1>;
1401 #size-cells = <0>;
1405 #address-cells = <1>;
1406 #size-cells = <0>;
1410 #address-cells = <1>;
1411 #size-cells = <0>;
1415 remote-endpoint = <&vp0_out_dsi1>;
1420 remote-endpoint = <&vp1_out_dsi1>;
1427 compatible = "rockchip,rk3568-dw-hdmi";
1435 clock-names = "iahb", "isfr", "cec", "ref", "hclk";
1436 power-domains = <&power RK3568_PD_VO>;
1437 reg-io-width = <4>;
1439 #sound-dai-cells = <0>;
1440 pinctrl-names = "default";
1441 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
1445 #address-cells = <1>;
1446 #size-cells = <0>;
1450 #address-cells = <1>;
1451 #size-cells = <0>;
1455 remote-endpoint = <&vp0_out_hdmi>;
1459 remote-endpoint = <&vp1_out_hdmi>;
1466 compatible = "rockchip,rk3568-edp";
1471 clock-names = "dp", "pclk", "spdif", "hclk";
1473 reset-names = "dp", "apb";
1475 phy-names = "dp";
1476 power-domains = <&power RK3568_PD_VO>;
1480 #address-cells = <1>;
1481 #size-cells = <0>;
1485 #address-cells = <1>;
1486 #size-cells = <0>;
1490 remote-endpoint = <&vp0_out_edp>;
1495 remote-endpoint = <&vp1_out_edp>;
1637 compatible = "rockchip,rk3568-dw-mshc",
1638 "rockchip,rk3288-dw-mshc";
1641 max-frequency = <150000000>;
1644 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1645 fifo-depth = <0x100>;
1647 reset-names = "reset";
1652 compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
1653 #address-cells = <3>;
1654 #size-cells = <2>;
1655 bus-range = <0x0 0x1f>;
1658 clock-names = "aclk_mst", "aclk_slv",
1666 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1667 linux,pci-domain = <0>;
1668 num-ib-windows = <6>;
1669 num-ob-windows = <2>;
1670 max-link-speed = <2>;
1671 msi-map = <0x0 &its 0x0 0x1000>;
1672 num-lanes = <1>;
1674 phy-names = "pcie-phy";
1675 power-domains = <&power RK3568_PD_PIPE>;
1682 reg-names = "pcie-dbi", "pcie-apb";
1684 reset-names = "pipe";
1689 compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
1690 #address-cells = <3>;
1691 #size-cells = <2>;
1692 bus-range = <0x0 0x1f>;
1695 clock-names = "aclk_mst", "aclk_slv",
1703 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1704 linux,pci-domain = <1>;
1705 num-ib-windows = <6>;
1706 num-ob-windows = <2>;
1707 max-link-speed = <3>;
1708 msi-map = <0x0 &its 0x3000 0x1000>;
1709 num-lanes = <1>;
1711 phy-names = "pcie-phy";
1712 power-domains = <&power RK3568_PD_PIPE>;
1719 reg-names = "pcie-dbi", "pcie-apb";
1721 reset-names = "pipe";
1727 compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
1728 #address-cells = <3>;
1729 #size-cells = <2>;
1730 bus-range = <0x0 0x1f>;
1733 clock-names = "aclk_mst", "aclk_slv",
1741 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1742 linux,pci-domain = <2>;
1743 num-ib-windows = <6>;
1744 num-ob-windows = <2>;
1745 max-link-speed = <3>;
1746 msi-map = <0x0 &its 0x2000 0x1000>;
1747 num-lanes = <2>;
1749 phy-names = "pcie-phy";
1750 power-domains = <&power RK3568_PD_PIPE>;
1757 reg-names = "pcie-dbi", "pcie-apb";
1759 reset-names = "pipe";
1765 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
1769 interrupt-names = "macirq", "eth_wake_irq";
1775 clock-names = "stmmaceth", "mac_clk_rx",
1780 reset-names = "stmmaceth";
1782 snps,mixed-burst;
1785 snps,axi-config = <&gmac0_stmmac_axi_setup>;
1786 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
1787 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
1791 compatible = "snps,dwmac-mdio";
1792 #address-cells = <0x1>;
1793 #size-cells = <0x0>;
1796 gmac0_stmmac_axi_setup: stmmac-axi-config {
1802 gmac0_mtl_rx_setup: rx-queues-config {
1803 snps,rx-queues-to-use = <1>;
1807 gmac0_mtl_tx_setup: tx-queues-config {
1808 snps,tx-queues-to-use = <1>;
1814 compatible = "rockchip,rk3568-dw-mshc",
1815 "rockchip,rk3288-dw-mshc";
1818 max-frequency = <150000000>;
1821 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1822 fifo-depth = <0x100>;
1824 reset-names = "reset";
1825 pinctrl-names = "default";
1826 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
1831 compatible = "rockchip,rk3568-dw-mshc",
1832 "rockchip,rk3288-dw-mshc";
1835 max-frequency = <150000000>;
1838 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1839 fifo-depth = <0x100>;
1841 reset-names = "reset";
1850 clock-names = "clk_sfc", "hclk_sfc";
1851 assigned-clocks = <&cru SCLK_SFC>;
1852 assigned-clock-rates = <100000000>;
1857 compatible = "rockchip,dwcmshc-sdhci", "snps,dwcmshc-sdhci";
1859 max-frequency = <200000000>;
1861 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
1862 assigned-clock-rates = <200000000>, <24000000>;
1866 clock-names = "core", "bus", "axi", "block", "timer";
1871 compatible = "rockchip,rk-nandc";
1876 clock-names = "clk_nandc", "hclk_nandc";
1881 compatible = "rockchip,rk3568-crypto";
1884 clock-names = "sclk_crypto", "apkclk_crypto";
1885 clock-frequency = <150000000>, <300000000>;
1890 compatible = "rockchip,cryptov2-rng";
1896 compatible = "rockchip,rk3568-otp";
1898 #address-cells = <1>;
1899 #size-cells = <1>;
1902 clock-names = "usr", "sbpi", "apb", "phy";
1904 reset-names = "otp_phy";
1907 cpu_code: cpu-code@2 {
1910 otp_cpu_version: cpu-version@8 {
1914 mbist_vmin: mbist-vmin@9 {
1921 cpu_leakage: cpu-leakage@1a {
1924 log_leakage: log-leakage@1b {
1927 npu_leakage: npu-leakage@1c {
1930 gpu_leakage: gpu-leakage@1d {
1933 core_pvtm:core-pvtm@2a {
1936 cpu_tsadc_trim_l: cpu-tsadc-trim-l@2e {
1939 cpu_tsadc_trim_h: cpu-tsadc-trim-h@2f {
1943 gpu_tsadc_trim_l: npu-tsadc-trim-l@30 {
1946 gpu_tsadc_trim_h: npu-tsadc-trim-h@31 {
1950 tsadc_trim_base_frac: tsadc-trim-base-frac@31 {
1954 tsadc_trim_base: tsadc-trim-base@32 {
1957 cpu_opp_info: cpu-opp-info@36 {
1960 gpu_opp_info: gpu-opp-info@3c {
1963 npu_opp_info: npu-opp-info@42 {
1966 dmc_opp_info: dmc-opp-info@48 {
1972 compatible = "rockchip,rk3568-i2s-tdm";
1976 clock-names = "mclk_tx", "mclk_rx", "hclk";
1978 dma-names = "tx";
1980 reset-names = "tx-m", "rx-m";
1983 rockchip,playback-only;
1984 #sound-dai-cells = <0>;
1989 compatible = "rockchip,rk3568-i2s-tdm";
1993 clock-names = "mclk_tx", "mclk_rx", "hclk";
1995 dma-names = "tx", "rx";
1997 reset-names = "tx-m", "rx-m";
2000 #sound-dai-cells = <0>;
2001 pinctrl-names = "default";
2002 pinctrl-0 = <&i2s1sclktxm0
2018 compatible = "rockchip,rk3568-i2s-tdm";
2022 clock-names = "mclk_tx", "mclk_rx", "hclk";
2024 dma-names = "tx", "rx";
2027 rockchip,clk-trcm = <1>;
2028 #sound-dai-cells = <0>;
2029 pinctrl-names = "default";
2030 pinctrl-0 = <&i2s2sclktxm0
2038 compatible = "rockchip,rk3568-i2s-tdm";
2042 clock-names = "mclk_tx", "mclk_rx", "hclk";
2044 dma-names = "tx", "rx";
2046 reset-names = "tx-m", "rx-m";
2049 #sound-dai-cells = <0>;
2050 pinctrl-names = "default";
2051 pinctrl-0 = <&i2s3sclkm0
2059 compatible = "rockchip,rk3568-pdm", "rockchip,pdm";
2062 clock-names = "pdm_clk", "pdm_hclk";
2064 dma-names = "rx";
2065 #sound-dai-cells = <0>;
2070 compatible = "rockchip,rk3568-vad";
2072 reg-names = "vad";
2074 clock-names = "hclk";
2076 rockchip,audio-src = <0>;
2077 rockchip,det-channel = <0>;
2079 #sound-dai-cells = <0>;
2084 compatible = "rockchip,rk3568-spdif";
2088 dma-names = "tx";
2089 clock-names = "mclk", "hclk";
2091 #sound-dai-cells = <0>;
2092 pinctrl-names = "default";
2093 pinctrl-0 = <&spdifm0_pins>;
2098 compatible = "rockchip,rk3568-audio-pwm", "rockchip,audio-pwm-v1";
2101 clock-names = "clk", "hclk";
2103 dma-names = "tx";
2104 #sound-dai-cells = <0>;
2105 rockchip,sample-width-bits = <11>;
2106 rockchip,interpolat-points = <1>;
2110 dig_acodec: codec-digital@fe478000 {
2111 compatible = "rockchip,rk3568-codec-digital", "rockchip,codec-digital-v1";
2115 clock-names = "adc", "dac", "i2c", "pclk";
2116 pinctrl-names = "default";
2117 pinctrl-0 = <&acodec_pins>;
2119 reset-names = "reset" ;
2121 #sound-dai-cells = <0>;
2131 clock-names = "apb_pclk";
2132 #dma-cells = <1>;
2133 arm,pl330-periph-burst;
2142 clock-names = "apb_pclk";
2143 #dma-cells = <1>;
2144 arm,pl330-periph-burst;
2148 compatible = "rockchip,canfd-1.0";
2152 clock-names = "baudclk", "apb_pclk";
2154 reset-names = "can", "can-apb";
2155 tx-fifo-depth = <1>;
2156 rx-fifo-depth = <6>;
2161 compatible = "rockchip,canfd-1.0";
2165 clock-names = "baudclk", "apb_pclk";
2167 reset-names = "can", "can-apb";
2168 tx-fifo-depth = <1>;
2169 rx-fifo-depth = <6>;
2174 compatible = "rockchip,canfd-1.0";
2178 clock-names = "baudclk", "apb_pclk";
2180 reset-names = "can", "can-apb";
2181 tx-fifo-depth = <1>;
2182 rx-fifo-depth = <6>;
2187 compatible = "rockchip,rk3399-i2c";
2190 clock-names = "i2c", "pclk";
2192 pinctrl-names = "default";
2193 pinctrl-0 = <&i2c1_xfer>;
2194 #address-cells = <1>;
2195 #size-cells = <0>;
2200 compatible = "rockchip,rk3399-i2c";
2203 clock-names = "i2c", "pclk";
2205 pinctrl-names = "default";
2206 pinctrl-0 = <&i2c2m0_xfer>;
2207 #address-cells = <1>;
2208 #size-cells = <0>;
2213 compatible = "rockchip,rk3399-i2c";
2216 clock-names = "i2c", "pclk";
2218 pinctrl-names = "default";
2219 pinctrl-0 = <&i2c3m0_xfer>;
2220 #address-cells = <1>;
2221 #size-cells = <0>;
2226 compatible = "rockchip,rk3399-i2c";
2229 clock-names = "i2c", "pclk";
2231 pinctrl-names = "default";
2232 pinctrl-0 = <&i2c4m0_xfer>;
2233 #address-cells = <1>;
2234 #size-cells = <0>;
2239 compatible = "rockchip,rk3399-i2c";
2242 clock-names = "i2c", "pclk";
2244 pinctrl-names = "default";
2245 pinctrl-0 = <&i2c5m0_xfer>;
2246 #address-cells = <1>;
2247 #size-cells = <0>;
2252 compatible = "snps,dw-wdt";
2255 clock-names = "tclk", "pclk";
2258 reset-names = "reset";
2263 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
2266 #address-cells = <1>;
2267 #size-cells = <0>;
2269 clock-names = "spiclk", "apb_pclk";
2271 dma-names = "tx", "rx";
2272 pinctrl-names = "default", "high_speed";
2273 pinctrl-0 = <&spi0clkm0 &spi0cs0m0 &spi0cs1m0 &spi0misom0 &spi0mosim0>;
2274 pinctrl-1 = <&spi0clkm0_hs &spi0cs0m0 &spi0cs1m0 &spi0misom0_hs &spi0mosim0_hs>;
2279 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
2282 #address-cells = <1>;
2283 #size-cells = <0>;
2285 clock-names = "spiclk", "apb_pclk";
2287 dma-names = "tx", "rx";
2288 pinctrl-names = "default", "high_speed";
2289 pinctrl-0 = <&spi1clkm0 &spi1cs0m0 &spi1cs1m0 &spi1misom0 &spi1mosim0>;
2290 pinctrl-1 = <&spi1clkm0_hs &spi1cs0m0 &spi1cs1m0 &spi1misom0_hs &spi1mosim0_hs>;
2295 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
2298 #address-cells = <1>;
2299 #size-cells = <0>;
2301 clock-names = "spiclk", "apb_pclk";
2303 dma-names = "tx", "rx";
2304 pinctrl-names = "default", "high_speed";
2305 pinctrl-0 = <&spi2clkm0 &spi2cs0m0 &spi2cs1m0 &spi2misom0 &spi2mosim0>;
2306 pinctrl-1 = <&spi2clkm0_hs &spi2cs0m0 &spi2cs1m0 &spi2misom0_hs &spi2mosim0_hs>;
2311 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
2314 #address-cells = <1>;
2315 #size-cells = <0>;
2317 clock-names = "spiclk", "apb_pclk";
2319 dma-names = "tx", "rx";
2320 pinctrl-names = "default", "high_speed";
2321 pinctrl-0 = <&spi3clkm0 &spi3cs0m0 &spi3cs1m0 &spi3misom0 &spi3mosim0>;
2322 pinctrl-1 = <&spi3clkm0_hs &spi3cs0m0 &spi3cs1m0 &spi3misom0_hs &spi3mosim0_hs>;
2327 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
2331 clock-names = "baudclk", "apb_pclk";
2332 reg-shift = <2>;
2333 reg-io-width = <4>;
2335 pinctrl-names = "default";
2336 pinctrl-0 = <&uart1m0_xfer>;
2341 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
2345 clock-names = "baudclk", "apb_pclk";
2346 reg-shift = <2>;
2347 reg-io-width = <4>;
2349 pinctrl-names = "default";
2350 pinctrl-0 = <&uart2m0_xfer>;
2355 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
2359 clock-names = "baudclk", "apb_pclk";
2360 reg-shift = <2>;
2361 reg-io-width = <4>;
2363 pinctrl-names = "default";
2364 pinctrl-0 = <&uart3m0_xfer>;
2369 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
2373 clock-names = "baudclk", "apb_pclk";
2374 reg-shift = <2>;
2375 reg-io-width = <4>;
2377 pinctrl-names = "default";
2378 pinctrl-0 = <&uart4m0_xfer>;
2383 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
2387 clock-names = "baudclk", "apb_pclk";
2388 reg-shift = <2>;
2389 reg-io-width = <4>;
2391 pinctrl-names = "default";
2392 pinctrl-0 = <&uart5m0_xfer>;
2397 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
2401 clock-names = "baudclk", "apb_pclk";
2402 reg-shift = <2>;
2403 reg-io-width = <4>;
2405 pinctrl-names = "default";
2406 pinctrl-0 = <&uart6m0_xfer>;
2411 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
2415 clock-names = "baudclk", "apb_pclk";
2416 reg-shift = <2>;
2417 reg-io-width = <4>;
2419 pinctrl-names = "default";
2420 pinctrl-0 = <&uart7m0_xfer>;
2425 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
2429 clock-names = "baudclk", "apb_pclk";
2430 reg-shift = <2>;
2431 reg-io-width = <4>;
2433 pinctrl-names = "default";
2434 pinctrl-0 = <&uart8m0_xfer>;
2439 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
2443 clock-names = "baudclk", "apb_pclk";
2444 reg-shift = <2>;
2445 reg-io-width = <4>;
2447 pinctrl-names = "default";
2448 pinctrl-0 = <&uart9m0_xfer>;
2452 pwm4: pwm@fe6e0000 {
2453 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
2455 #pwm-cells = <3>;
2456 pinctrl-names = "active";
2457 pinctrl-0 = <&pwm4_pins>;
2459 clock-names = "pwm", "pclk";
2463 pwm5: pwm@fe6e0010 {
2464 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
2466 #pwm-cells = <3>;
2467 pinctrl-names = "active";
2468 pinctrl-0 = <&pwm5_pins>;
2470 clock-names = "pwm", "pclk";
2474 pwm6: pwm@fe6e0020 {
2475 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
2477 #pwm-cells = <3>;
2478 pinctrl-names = "active";
2479 pinctrl-0 = <&pwm6_pins>;
2481 clock-names = "pwm", "pclk";
2485 pwm7: pwm@fe6e0030 {
2486 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
2488 #pwm-cells = <3>;
2489 pinctrl-names = "active";
2490 pinctrl-0 = <&pwm7_pins>;
2492 clock-names = "pwm", "pclk";
2496 pwm8: pwm@fe6f0000 {
2497 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
2499 #pwm-cells = <3>;
2500 pinctrl-names = "active";
2501 pinctrl-0 = <&pwm8m0_pins>;
2503 clock-names = "pwm", "pclk";
2507 pwm9: pwm@fe6f0010 {
2508 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
2510 #pwm-cells = <3>;
2511 pinctrl-names = "active";
2512 pinctrl-0 = <&pwm9m0_pins>;
2514 clock-names = "pwm", "pclk";
2518 pwm10: pwm@fe6f0020 {
2519 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
2521 #pwm-cells = <3>;
2522 pinctrl-names = "active";
2523 pinctrl-0 = <&pwm10m0_pins>;
2525 clock-names = "pwm", "pclk";
2529 pwm11: pwm@fe6f0030 {
2530 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
2532 #pwm-cells = <3>;
2533 pinctrl-names = "active";
2534 pinctrl-0 = <&pwm11m0_pins>;
2536 clock-names = "pwm", "pclk";
2540 pwm12: pwm@fe700000 {
2541 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
2543 #pwm-cells = <3>;
2544 pinctrl-names = "active";
2545 pinctrl-0 = <&pwm12m0_pins>;
2547 clock-names = "pwm", "pclk";
2551 pwm13: pwm@fe700010 {
2552 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
2554 #pwm-cells = <3>;
2555 pinctrl-names = "active";
2556 pinctrl-0 = <&pwm13m0_pins>;
2558 clock-names = "pwm", "pclk";
2562 pwm14: pwm@fe700020 {
2563 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
2565 #pwm-cells = <3>;
2566 pinctrl-names = "active";
2567 pinctrl-0 = <&pwm14m0_pins>;
2569 clock-names = "pwm", "pclk";
2573 pwm15: pwm@fe700030 {
2574 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
2576 #pwm-cells = <3>;
2577 pinctrl-names = "active";
2578 pinctrl-0 = <&pwm15m0_pins>;
2580 clock-names = "pwm", "pclk";
2585 compatible = "rockchip,rk3568-tsadc";
2590 clock-names = "tsadc", "apb_pclk";
2591 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
2592 assigned-clock-rates = <17000000>, <700000>;
2595 reset-names = "tsadc", "tsadc-apb", "tsadc-phy";
2596 #thermal-sensor-cells = <1>;
2597 rockchip,hw-tshut-temp = <120000>;
2598 rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
2599 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
2600 pinctrl-names = "gpio", "otpout";
2601 pinctrl-0 = <&tsadc_gpio>;
2602 pinctrl-1 = <&tsadc_shutorg>;
2607 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
2610 #io-channel-cells = <1>;
2612 clock-names = "saradc", "apb_pclk";
2614 reset-names = "saradc-apb";
2619 compatible = "rockchip,rk3568-mailbox",
2620 "rockchip,rk3368-mailbox";
2627 clock-names = "pclk_mailbox";
2628 #mbox-cells = <1>;
2633 compatible = "rockchip,rk3568-naneng-combphy";
2635 #phy-cells = <1>;
2637 clock-names = "refclk", "apbclk";
2638 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
2639 assigned-clock-rates = <24000000>;
2641 reset-names = "combphy-apb", "combphy";
2642 rockchip,pipe-grf = <&pipegrf>;
2643 rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
2648 compatible = "rockchip,rk3568-naneng-combphy";
2650 #phy-cells = <1>;
2652 clock-names = "refclk", "apbclk";
2653 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
2654 assigned-clock-rates = <24000000>;
2656 reset-names = "combphy-apb", "combphy";
2657 rockchip,pipe-grf = <&pipegrf>;
2658 rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
2663 compatible = "rockchip,rk3568-naneng-combphy";
2665 #phy-cells = <1>;
2667 clock-names = "refclk", "apbclk";
2668 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
2669 assigned-clock-rates = <24000000>;
2671 reset-names = "combphy-apb", "combphy";
2672 rockchip,pipe-grf = <&pipegrf>;
2673 rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
2677 mipi_dphy0: mipi-dphy@fe850000 {
2678 compatible = "rockchip,rk3568-mipi-dphy";
2681 clock-names = "ref", "pclk";
2682 clock-output-names = "mipi_dphy_pll";
2683 #clock-cells = <0>;
2685 reset-names = "apb";
2686 power-domains = <&power RK3568_PD_VO>;
2687 #phy-cells = <0>;
2692 video_phy0: video-phy@fe850000 {
2693 compatible = "rockchip,rk3568-video-phy";
2698 clock-names = "ref", "pclk_phy", "pclk_host";
2699 #clock-cells = <0>;
2701 reset-names = "rst";
2702 power-domains = <&power RK3568_PD_VO>;
2703 #phy-cells = <0>;
2707 mipi_dphy1: mipi-dphy@fe860000 {
2708 compatible = "rockchip,rk3568-mipi-dphy";
2711 clock-names = "ref", "pclk";
2712 clock-output-names = "mipi_dphy1_pll";
2713 #clock-cells = <0>;
2715 reset-names = "apb";
2716 power-domains = <&power RK3568_PD_VO>;
2717 #phy-cells = <0>;
2722 video_phy1: video-phy@fe860000 {
2723 compatible = "rockchip,rk3568-video-phy";
2728 clock-names = "ref", "pclk_phy", "pclk_host";
2729 #clock-cells = <0>;
2731 reset-names = "rst";
2732 power-domains = <&power RK3568_PD_VO>;
2733 #phy-cells = <0>;
2737 csi_dphy: csi-dphy@fe870000 {
2738 compatible = "rockchip,rk3568-csi-dphy";
2741 clock-names = "pclk";
2746 usb2phy0: usb2-phy@fe8a0000 {
2747 compatible = "rockchip,rk3568-usb2phy";
2751 clock-names = "phyclk";
2752 #clock-cells = <0>;
2753 assigned-clocks = <&cru USB480M>;
2754 assigned-clock-parents = <&usb2phy0>;
2755 clock-output-names = "usb480m_phy";
2759 u2phy0_host: host-port {
2760 #phy-cells = <0>;
2764 u2phy0_otg: otg-port {
2765 #phy-cells = <0>;
2770 usb2phy1: usb2-phy@fe8b0000 {
2771 compatible = "rockchip,rk3568-usb2phy";
2775 clock-names = "phyclk";
2776 #clock-cells = <0>;
2780 u2phy1_host: host-port {
2781 #phy-cells = <0>;
2785 u2phy1_otg: otg-port {
2786 #phy-cells = <0>;
2792 compatible = "rockchip,rk3568-pcie3-phy";
2794 #phy-cells = <0>;
2797 clock-names = "refclk_m", "refclk_n", "pclk";
2799 reset-names = "phy";
2800 rockchip,phy-grf = <&pcie30_phy_grf>;
2805 compatible = "rockchip,rk3568-pinctrl";
2808 #address-cells = <2>;
2809 #size-cells = <2>;
2813 compatible = "rockchip,gpio-bank";
2818 gpio-controller;
2819 #gpio-cells = <2>;
2820 gpio-ranges = <&pinctrl 0 0 32>;
2821 interrupt-controller;
2822 #interrupt-cells = <2>;
2826 compatible = "rockchip,gpio-bank";
2831 gpio-controller;
2832 #gpio-cells = <2>;
2833 gpio-ranges = <&pinctrl 0 32 32>;
2834 interrupt-controller;
2835 #interrupt-cells = <2>;
2839 compatible = "rockchip,gpio-bank";
2844 gpio-controller;
2845 #gpio-cells = <2>;
2846 gpio-ranges = <&pinctrl 0 64 32>;
2847 interrupt-controller;
2848 #interrupt-cells = <2>;
2852 compatible = "rockchip,gpio-bank";
2857 gpio-controller;
2858 #gpio-cells = <2>;
2859 gpio-ranges = <&pinctrl 0 96 32>;
2860 interrupt-controller;
2861 #interrupt-cells = <2>;
2865 compatible = "rockchip,gpio-bank";
2870 gpio-controller;
2871 #gpio-cells = <2>;
2872 gpio-ranges = <&pinctrl 0 128 32>;
2873 interrupt-controller;
2874 #interrupt-cells = <2>;
2879 #include "rk3568-pinctrl.dtsi"