Lines Matching +full:0 +full:xfe400000
58 #size-cells = <0>;
60 cpu0: cpu@0 {
63 reg = <0x0 0x0>;
72 reg = <0x0 0x100>;
81 reg = <0x0 0x200>;
90 reg = <0x0 0x300>;
160 thermal-sensors = <&tsadc 0>;
192 #clock-cells = <0>;
199 #clock-cells = <0>;
204 #clock-cells = <0>;
211 reg = <0 0xfc000000 0 0x1000>;
219 ports-implemented = <0x1>;
226 reg = <0 0xfc400000 0 0x1000>;
234 ports-implemented = <0x1>;
241 reg = <0 0xfc800000 0 0x1000>;
249 ports-implemented = <0x1>;
267 reg = <0x0 0xfcc00000 0x0 0x400000>;
299 reg = <0x0 0xfd000000 0x0 0x400000>;
326 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
327 <0x0 0xfd460000 0 0xc0000>; /* GICR */
332 reg = <0x0 0xfd440000 0x0 0x20000>;
339 reg = <0x0 0xfd800000 0x0 0x40000>;
351 reg = <0x0 0xfd840000 0x0 0x40000>;
363 reg = <0x0 0xfd880000 0x0 0x40000>;
375 reg = <0x0 0xfd8c0000 0x0 0x40000>;
387 reg = <0x0 0xfdc20000 0x0 0x10000>;
396 offset = <0x200>;
411 reg = <0x0 0xfdc50000 0x0 0x1000>;
416 reg = <0x0 0xfdc60000 0x0 0x10000>;
431 #size-cells = <0>;
433 port@0 {
434 reg = <0>;
436 #size-cells = <0>;
438 lvds0_in_vp1: endpoint@0 {
439 reg = <0>;
459 #size-cells = <0>;
461 port@0 {
462 reg = <0>;
464 #size-cells = <0>;
466 lvds1_in_vp1: endpoint@0 {
467 reg = <0>;
482 pinctrl-0 = <&lcdc_ctl>;
487 #size-cells = <0>;
489 port@0 {
490 reg = <0>;
492 #size-cells = <0>;
494 rgb_in_vp2: endpoint@0 {
495 reg = <0>;
507 reg = <0x0 0xfdc70000 0x0 0x1000>;
512 reg = <0x0 0xfdc80000 0x0 0x1000>;
517 reg = <0x0 0xfdc90000 0x0 0x1000>;
522 reg = <0x0 0xfdca0000 0x0 0x8000>;
527 reg = <0x0 0xfdca8000 0x0 0x8000>;
532 reg = <0x0 0xfdcb0000 0x0 0x8000>;
537 #phy-cells = <0>;
543 reg = <0x0 0xfdcb8000 0x0 0x10000>;
548 reg = <0x0 0xfdd00000 0x0 0x1000>;
556 reg = <0x0 0xfdd20000 0x0 0x1000>;
585 reg = <0x0 0xfdd40000 0x0 0x1000>;
590 pinctrl-0 = <&i2c0_xfer>;
592 #size-cells = <0>;
598 reg = <0x0 0xfdd50000 0x0 0x100>;
604 dmas = <&dmac0 0>, <&dmac0 1>;
606 pinctrl-0 = <&uart0_xfer>;
612 reg = <0x0 0xfdd70000 0x0 0x10>;
615 pinctrl-0 = <&pwm0m0_pins>;
623 reg = <0x0 0xfdd70010 0x0 0x10>;
626 pinctrl-0 = <&pwm1m0_pins>;
634 reg = <0x0 0xfdd70020 0x0 0x10>;
637 pinctrl-0 = <&pwm2m0_pins>;
645 reg = <0x0 0xfdd70030 0x0 0x10>;
648 pinctrl-0 = <&pwm3_pins>;
656 reg = <0x0 0xfdd90000 0x0 0x1000>;
662 #size-cells = <0>;
743 reg = <0x0 0xfde00000 0x0 0x100>;
745 #size-cells = <0>;
746 pvtm@0 {
747 reg = <0>;
758 reg = <0x0 0xfde60000 0x0 0x4000>;
807 reg = <0x0 0xfde80000 0x0 0x100>;
809 #size-cells = <0>;
822 reg = <0x0 0xfde90000 0x0 0x100>;
824 #size-cells = <0>;
838 reg = <0x0 0xfdea0400 0x0 0x400>;
848 rockchip,taskqueue-node = <0>;
849 rockchip,resetgroup-node = <0>;
855 reg = <0x0 0xfdea0800 0x0 0x40>;
861 #iommu-cells = <0>;
867 reg = <0x0 0xfdeb0000 0x0 0x1000>;
877 reg = <0x0 0xfdec0000 0x0 0x5000>;
884 pinctrl-0 = <&ebc_pins>;
890 reg = <0x0 0xfded0000 0x0 0x400>;
894 rockchip,normal-rates = <297000000>, <0>;
907 reg = <0x0 0xfded0480 0x0 0x40>;
913 #iommu-cells = <0>;
919 reg = <0x0 0xfdee0000 0x0 0x400>;
923 rockchip,normal-rates = <297000000>, <0>;
936 reg = <0x0 0xfdee0800 0x0 0x40>;
942 #iommu-cells = <0>;
948 reg = <0x0 0xfdef0000 0x0 0x500>;
965 reg = <0x0 0xfdef0800 0x0 0x100>;
970 #iommu-cells = <0>;
978 reg = <0x0 0xfdf00000 0x0 0x74>;
987 reg = <0x0 0xfdf40000 0x0 0x400>;
993 rockchip,normal-rates = <297000000>, <0>, <400000000>;
994 rockchip,advanced-rates = <297000000>, <0>, <500000000>;
1012 reg = <0x0 0xfdf40f00 0x0 0x40>, <0x0 0xfdf40f40 0x0 0x40>;
1020 #iommu-cells = <0>;
1027 reg = <0x0 0xfdf80200 0x0 0x400>;
1035 rockchip,normal-rates = <297000000>, <0>, <297000000>,
1037 rockchip,advanced-rates = <400000000>, <0>, <400000000>,
1058 reg = <0x0 0xfdf80800 0x0 0x40>, <0x0 0xfdf80840 0x0 0x40>;
1064 #iommu-cells = <0>;
1070 reg = <0x0 0xfdfb0000 0x0 0x10000>;
1083 reg = <0x0 0xfdfe0000 0x0 0x8000>;
1108 reg = <0x0 0xfdfe0800 0x0 0x100>;
1114 #iommu-cells = <0>;
1147 reg = <0x0 0xfdff0000 0x0 0x10000>;
1164 reg = <0x0 0xfdff1a00 0x0 0x100>;
1170 #iommu-cells = <0>;
1189 reg = <0x0 0xfe010000 0x0 0x10000>;
1215 #address-cells = <0x1>;
1216 #size-cells = <0x0>;
1222 snps,blen = <0 0 0 0 16 8 4>;
1238 reg = <0x0 0xfe040000 0x0 0x3000>;
1250 #size-cells = <0>;
1252 port@0 {
1254 #size-cells = <0>;
1255 reg = <0>;
1257 vp0_out_dsi0: endpoint@0 {
1258 reg = <0>;
1280 #size-cells = <0>;
1283 vp1_out_dsi0: endpoint@0 {
1284 reg = <0>;
1317 #size-cells = <0>;
1321 vp2_out_lvds0: endpoint@0 {
1322 reg = <0>;
1341 reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
1346 #iommu-cells = <0>;
1352 reg = <0x0 0xfe060000 0x0 0x10000>;
1363 #size-cells = <0>;
1368 #size-cells = <0>;
1370 dsi0_in: port@0 {
1371 reg = <0>;
1373 #size-cells = <0>;
1375 dsi0_in_vp0: endpoint@0 {
1376 reg = <0>;
1390 reg = <0x0 0xfe070000 0x0 0x10000>;
1401 #size-cells = <0>;
1406 #size-cells = <0>;
1408 dsi1_in: port@0 {
1409 reg = <0>;
1411 #size-cells = <0>;
1413 dsi1_in_vp0: endpoint@0 {
1414 reg = <0>;
1428 reg = <0x0 0xfe0a0000 0x0 0x20000>;
1439 #sound-dai-cells = <0>;
1441 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
1446 #size-cells = <0>;
1449 reg = <0>;
1451 #size-cells = <0>;
1453 hdmi_in_vp0: endpoint@0 {
1454 reg = <0>;
1467 reg = <0x0 0xfe0c0000 0x0 0x10000>;
1481 #size-cells = <0>;
1483 edp_in: port@0 {
1484 reg = <0>;
1486 #size-cells = <0>;
1488 edp_in_vp0: endpoint@0 {
1489 reg = <0>;
1503 reg = <0x0 0xfe128000 0x0 0x20>;
1508 reg = <0x0 0xfe138080 0x0 0x20>;
1513 reg = <0x0 0xfe138100 0x0 0x20>;
1518 reg = <0x0 0xfe138180 0x0 0x20>;
1523 reg = <0x0 0xfe148000 0x0 0x20>;
1528 reg = <0x0 0xfe148080 0x0 0x20>;
1533 reg = <0x0 0xfe148100 0x0 0x20>;
1538 reg = <0x0 0xfe150000 0x0 0x20>;
1543 reg = <0x0 0xfe158000 0x0 0x20>;
1548 reg = <0x0 0xfe158100 0x0 0x20>;
1553 reg = <0x0 0xfe158180 0x0 0x20>;
1558 reg = <0x0 0xfe158200 0x0 0x20>;
1563 reg = <0x0 0xfe158280 0x0 0x20>;
1568 reg = <0x0 0xfe158300 0x0 0x20>;
1573 reg = <0x0 0xfe180000 0x0 0x20>;
1578 reg = <0x0 0xfe190000 0x0 0x20>;
1583 reg = <0x0 0xfe190080 0x0 0x20>;
1588 reg = <0x0 0xfe190100 0x0 0x20>;
1593 reg = <0x0 0xfe190200 0x0 0x20>;
1598 reg = <0x0 0xfe190280 0x0 0x20>;
1603 reg = <0x0 0xfe190300 0x0 0x20>;
1608 reg = <0x0 0xfe190380 0x0 0x20>;
1613 reg = <0x0 0xfe190400 0x0 0x20>;
1618 reg = <0x0 0xfe198000 0x0 0x20>;
1623 reg = <0x0 0xfe1a8000 0x0 0x20>;
1628 reg = <0x0 0xfe1a8080 0x0 0x20>;
1633 reg = <0x0 0xfe1a8100 0x0 0x20>;
1639 reg = <0x0 0xfe000000 0x0 0x4000>;
1645 fifo-depth = <0x100>;
1655 bus-range = <0x0 0x1f>;
1667 linux,pci-domain = <0>;
1671 msi-map = <0x0 &its 0x0 0x1000>;
1676 ranges = <0x00000800 0x0 0xf4000000 0x0 0xf4000000 0x0 0x100000
1677 0x81000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x100000
1678 0x82000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x1e00000
1679 0xc3000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>;
1680 reg = <0x3 0xc0000000 0x0 0x400000>,
1681 <0x0 0xfe260000 0x0 0x10000>;
1692 bus-range = <0x0 0x1f>;
1708 msi-map = <0x0 &its 0x3000 0x1000>;
1713 ranges = <0x00000800 0x0 0xf2000000 0x0 0xf2000000 0x0 0x100000
1714 0x81000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x100000
1715 0x82000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x1e00000
1716 0xc3000000 0x3 0x40000000 0x3 0x40000000 0x0 0x40000000>;
1717 reg = <0x3 0xc0400000 0x0 0x400000>,
1718 <0x0 0xfe270000 0x0 0x10000>;
1730 bus-range = <0x0 0x1f>;
1746 msi-map = <0x0 &its 0x2000 0x1000>;
1751 ranges = <0x00000800 0x0 0xf0000000 0x0 0xf0000000 0x0 0x100000
1752 0x81000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x100000
1753 0x82000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x1e00000
1754 0xc3000000 0x3 0x80000000 0x3 0x80000000 0x0 0x40000000>;
1755 reg = <0x3 0xc0800000 0x0 0x400000>,
1756 <0x0 0xfe280000 0x0 0x10000>;
1766 reg = <0x0 0xfe2a0000 0x0 0x10000>;
1792 #address-cells = <0x1>;
1793 #size-cells = <0x0>;
1799 snps,blen = <0 0 0 0 16 8 4>;
1816 reg = <0x0 0xfe2b0000 0x0 0x4000>;
1822 fifo-depth = <0x100>;
1826 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
1833 reg = <0x0 0xfe2c0000 0x0 0x4000>;
1839 fifo-depth = <0x100>;
1847 reg = <0x0 0xfe300000 0x0 0x4000>;
1858 reg = <0x0 0xfe310000 0x0 0x10000>;
1872 reg = <0x0 0xfe330000 0x0 0x4000>;
1874 nandc_id = <0>;
1882 reg = <0x0 0xfe380000 0x0 0x4000>;
1891 reg = <0x0 0xfe388000 0x0 0x2000>;
1897 reg = <0x0 0xfe38c000 0x0 0x4000>;
1908 reg = <0x02 0x2>;
1911 reg = <0x08 0x1>;
1915 reg = <0x09 0x1>;
1916 bits = <0 4>;
1919 reg = <0x0a 0x10>;
1922 reg = <0x1a 0x1>;
1925 reg = <0x1b 0x1>;
1928 reg = <0x1c 0x1>;
1931 reg = <0x1d 0x1>;
1934 reg = <0x2a 0x2>;
1937 reg = <0x2e 0x1>;
1940 reg = <0x2f 0x1>;
1941 bits = <0 4>;
1944 reg = <0x30 0x1>;
1947 reg = <0x31 0x1>;
1948 bits = <0 4>;
1951 reg = <0x31 0x1>;
1955 reg = <0x32 0x1>;
1958 reg = <0x36 0x6>;
1961 reg = <0x3c 0x6>;
1964 reg = <0x42 0x6>;
1967 reg = <0x48 0x6>;
1973 reg = <0x0 0xfe400000 0x0 0x1000>;
1977 dmas = <&dmac1 0>;
1984 #sound-dai-cells = <0>;
1990 reg = <0x0 0xfe410000 0x0 0x1000>;
2000 #sound-dai-cells = <0>;
2002 pinctrl-0 = <&i2s1sclktxm0
2019 reg = <0x0 0xfe420000 0x0 0x1000>;
2028 #sound-dai-cells = <0>;
2030 pinctrl-0 = <&i2s2sclktxm0
2039 reg = <0x0 0xfe430000 0x0 0x1000>;
2049 #sound-dai-cells = <0>;
2051 pinctrl-0 = <&i2s3sclkm0
2060 reg = <0x0 0xfe440000 0x0 0x1000>;
2065 #sound-dai-cells = <0>;
2071 reg = <0x0 0xfe450000 0x0 0x10000>;
2076 rockchip,audio-src = <0>;
2077 rockchip,det-channel = <0>;
2078 rockchip,mode = <0>;
2079 #sound-dai-cells = <0>;
2085 reg = <0x0 0xfe460000 0x0 0x1000>;
2091 #sound-dai-cells = <0>;
2093 pinctrl-0 = <&spdifm0_pins>;
2099 reg = <0x0 0xfe470000 0x0 0x1000>;
2104 #sound-dai-cells = <0>;
2112 reg = <0x0 0xfe478000 0x0 0x1000>;
2117 pinctrl-0 = <&acodec_pins>;
2121 #sound-dai-cells = <0>;
2127 reg = <0x0 0xfe530000 0x0 0x4000>;
2138 reg = <0x0 0xfe550000 0x0 0x4000>;
2149 reg = <0x0 0xfe570000 0x0 0x1000>;
2162 reg = <0x0 0xfe580000 0x0 0x1000>;
2175 reg = <0x0 0xfe590000 0x0 0x1000>;
2188 reg = <0x0 0xfe5a0000 0x0 0x1000>;
2193 pinctrl-0 = <&i2c1_xfer>;
2195 #size-cells = <0>;
2201 reg = <0x0 0xfe5b0000 0x0 0x1000>;
2206 pinctrl-0 = <&i2c2m0_xfer>;
2208 #size-cells = <0>;
2214 reg = <0x0 0xfe5c0000 0x0 0x1000>;
2219 pinctrl-0 = <&i2c3m0_xfer>;
2221 #size-cells = <0>;
2227 reg = <0x0 0xfe5d0000 0x0 0x1000>;
2232 pinctrl-0 = <&i2c4m0_xfer>;
2234 #size-cells = <0>;
2240 reg = <0x0 0xfe5e0000 0x0 0x1000>;
2245 pinctrl-0 = <&i2c5m0_xfer>;
2247 #size-cells = <0>;
2253 reg = <0x0 0xfe600000 0x0 0x100>;
2264 reg = <0x0 0xfe610000 0x0 0x1000>;
2267 #size-cells = <0>;
2273 pinctrl-0 = <&spi0clkm0 &spi0cs0m0 &spi0cs1m0 &spi0misom0 &spi0mosim0>;
2280 reg = <0x0 0xfe620000 0x0 0x1000>;
2283 #size-cells = <0>;
2289 pinctrl-0 = <&spi1clkm0 &spi1cs0m0 &spi1cs1m0 &spi1misom0 &spi1mosim0>;
2296 reg = <0x0 0xfe630000 0x0 0x1000>;
2299 #size-cells = <0>;
2305 pinctrl-0 = <&spi2clkm0 &spi2cs0m0 &spi2cs1m0 &spi2misom0 &spi2mosim0>;
2312 reg = <0x0 0xfe640000 0x0 0x1000>;
2315 #size-cells = <0>;
2321 pinctrl-0 = <&spi3clkm0 &spi3cs0m0 &spi3cs1m0 &spi3misom0 &spi3mosim0>;
2328 reg = <0x0 0xfe650000 0x0 0x100>;
2336 pinctrl-0 = <&uart1m0_xfer>;
2342 reg = <0x0 0xfe660000 0x0 0x100>;
2350 pinctrl-0 = <&uart2m0_xfer>;
2356 reg = <0x0 0xfe670000 0x0 0x100>;
2364 pinctrl-0 = <&uart3m0_xfer>;
2370 reg = <0x0 0xfe680000 0x0 0x100>;
2378 pinctrl-0 = <&uart4m0_xfer>;
2384 reg = <0x0 0xfe690000 0x0 0x100>;
2392 pinctrl-0 = <&uart5m0_xfer>;
2398 reg = <0x0 0xfe6a0000 0x0 0x100>;
2406 pinctrl-0 = <&uart6m0_xfer>;
2412 reg = <0x0 0xfe6b0000 0x0 0x100>;
2420 pinctrl-0 = <&uart7m0_xfer>;
2426 reg = <0x0 0xfe6c0000 0x0 0x100>;
2434 pinctrl-0 = <&uart8m0_xfer>;
2440 reg = <0x0 0xfe6d0000 0x0 0x100>;
2448 pinctrl-0 = <&uart9m0_xfer>;
2454 reg = <0x0 0xfe6e0000 0x0 0x10>;
2457 pinctrl-0 = <&pwm4_pins>;
2465 reg = <0x0 0xfe6e0010 0x0 0x10>;
2468 pinctrl-0 = <&pwm5_pins>;
2476 reg = <0x0 0xfe6e0020 0x0 0x10>;
2479 pinctrl-0 = <&pwm6_pins>;
2487 reg = <0x0 0xfe6e0030 0x0 0x10>;
2490 pinctrl-0 = <&pwm7_pins>;
2498 reg = <0x0 0xfe6f0000 0x0 0x10>;
2501 pinctrl-0 = <&pwm8m0_pins>;
2509 reg = <0x0 0xfe6f0010 0x0 0x10>;
2512 pinctrl-0 = <&pwm9m0_pins>;
2520 reg = <0x0 0xfe6f0020 0x0 0x10>;
2523 pinctrl-0 = <&pwm10m0_pins>;
2531 reg = <0x0 0xfe6f0030 0x0 0x10>;
2534 pinctrl-0 = <&pwm11m0_pins>;
2542 reg = <0x0 0xfe700000 0x0 0x10>;
2545 pinctrl-0 = <&pwm12m0_pins>;
2553 reg = <0x0 0xfe700010 0x0 0x10>;
2556 pinctrl-0 = <&pwm13m0_pins>;
2564 reg = <0x0 0xfe700020 0x0 0x10>;
2567 pinctrl-0 = <&pwm14m0_pins>;
2575 reg = <0x0 0xfe700030 0x0 0x10>;
2578 pinctrl-0 = <&pwm15m0_pins>;
2586 reg = <0x0 0xfe710000 0x0 0x100>;
2598 rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
2599 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
2601 pinctrl-0 = <&tsadc_gpio>;
2608 reg = <0x0 0xfe720000 0x0 0x100>;
2621 reg = <0x0 0xfe780000 0x0 0x1000>;
2634 reg = <0x0 0xfe820000 0x0 0x100>;
2649 reg = <0x0 0xfe830000 0x0 0x100>;
2664 reg = <0x0 0xfe840000 0x0 0x100>;
2679 reg = <0x0 0xfe850000 0x0 0x10000>;
2683 #clock-cells = <0>;
2687 #phy-cells = <0>;
2694 reg = <0x0 0xfe850000 0x0 0x10000>,
2695 <0x0 0xfe060000 0x0 0x10000>;
2699 #clock-cells = <0>;
2703 #phy-cells = <0>;
2709 reg = <0x0 0xfe860000 0x0 0x10000>;
2713 #clock-cells = <0>;
2717 #phy-cells = <0>;
2724 reg = <0x0 0xfe860000 0x0 0x10000>,
2725 <0x0 0xfe070000 0x0 0x10000>;
2729 #clock-cells = <0>;
2733 #phy-cells = <0>;
2739 reg = <0x0 0xfe870000 0x0 0x1000>;
2748 reg = <0x0 0xfe8a0000 0x0 0x10000>;
2752 #clock-cells = <0>;
2760 #phy-cells = <0>;
2765 #phy-cells = <0>;
2772 reg = <0x0 0xfe8b0000 0x0 0x10000>;
2776 #clock-cells = <0>;
2781 #phy-cells = <0>;
2786 #phy-cells = <0>;
2793 reg = <0x0 0xfe8c0000 0x0 0x20000>;
2794 #phy-cells = <0>;
2814 reg = <0x0 0xfdd60000 0x0 0x100>;
2820 gpio-ranges = <&pinctrl 0 0 32>;
2827 reg = <0x0 0xfe740000 0x0 0x100>;
2833 gpio-ranges = <&pinctrl 0 32 32>;
2840 reg = <0x0 0xfe750000 0x0 0x100>;
2846 gpio-ranges = <&pinctrl 0 64 32>;
2853 reg = <0x0 0xfe760000 0x0 0x100>;
2859 gpio-ranges = <&pinctrl 0 96 32>;
2866 reg = <0x0 0xfe770000 0x0 0x100>;
2872 gpio-ranges = <&pinctrl 0 128 32>;