arm/dts/rk3568-spi-nand.dts

2  * SPDX-License-Identifier:     GPL-2.0+
7 /dts-v1/;
9 #include <dt-bindings/input/input.h>
13 	compatible = "rockchip,rk3568-evb", "rockchip,rk3568";
24 		stdout-path = &uart2;
25 		u-boot,spl-boot-order = &spi_nand;
28 	adc-keys {
29 		compatible = "adc-keys";
30 		io-channels = <&saradc 0>;
31 		io-channel-names = "buttons";
32 		keyup-threshold-microvolt = <1800000>;
33 		u-boot,dm-spl;
36 		volumeup-key {
37 			u-boot,dm-spl;
40 			press-threshold-microvolt = <9>;
46 	u-boot,dm-pre-reloc;
51 	clock-frequency = <24000000>;
52 	u-boot,dm-spl;
53 	/delete-property/ pinctrl-names;
54 	/delete-property/ pinctrl-0;
59 	u-boot,dm-pre-reloc;
64 	u-boot,dm-pre-reloc;
69 	u-boot,dm-pre-reloc;
74 	u-boot,dm-pre-reloc;
79 	u-boot,dm-pre-reloc;
84 	u-boot,dm-pre-reloc;
89 	u-boot,dm-pre-reloc;
94 	u-boot,dm-pre-reloc;
99 	u-boot,dm-pre-reloc;
104 	u-boot,dm-pre-reloc;
109 	u-boot,dm-pre-reloc;
114 	u-boot,dm-pre-reloc;
119 	u-boot,dm-pre-reloc;
123 	u-boot,dm-pre-reloc;
127 	u-boot,dm-pre-reloc;
128 	phy-mode = "rgmii";
131 	snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
132 	snps,reset-active-low;
134 	snps,reset-delays-us = <0 20000 100000>;
135 	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
136 	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
137 	assigned-clock-rates = <0>, <125000000>;
139 	pinctrl-names = "default";
140 	pinctrl-0 = <&gmac0_miim
149 	phy-handle = <&rgmii_phy0>;
154 	u-boot,dm-pre-reloc;
155 	phy-mode = "rgmii";
158 	snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
159 	snps,reset-active-low;
161 	snps,reset-delays-us = <0 20000 100000>;
163 	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
164 	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
165 	assigned-clock-rates = <0>, <125000000>;
167 	pinctrl-names = "default";
168 	pinctrl-0 = <&gmac1m1_miim
177 	phy-handle = <&rgmii_phy1>;
182 	u-boot,dm-pre-reloc;
186 	u-boot,dm-pre-reloc;
188 		u-boot,dm-pre-reloc;
193 	u-boot,dm-pre-reloc;
195 		u-boot,dm-pre-reloc;
200 	u-boot,dm-pre-reloc;
204 	u-boot,dm-pre-reloc;
206 		u-boot,dm-pre-reloc;
211 	u-boot,dm-pre-reloc;
213 		u-boot,dm-pre-reloc;
218 	u-boot,dm-pre-reloc;
220 		compatible = "ethernet-phy-ieee802.3-c22";
221 		u-boot,dm-pre-reloc;
227 	u-boot,dm-pre-reloc;
229 		compatible = "ethernet-phy-ieee802.3-c22";
230 		u-boot,dm-pre-reloc;
236 	u-boot,dm-pre-reloc;
240 	u-boot,dm-pre-reloc;
244 	u-boot,dm-pre-reloc;
248 	u-boot,dm-pre-reloc;
252 	u-boot,dm-pre-reloc;
256 	u-boot,dm-pre-reloc;
260 	u-boot,dm-pre-reloc;
264 	u-boot,dm-pre-reloc;
268 	u-boot,dm-pre-reloc;
272 	u-boot,dm-pre-reloc;
276 	u-boot,dm-pre-reloc;
280 	u-boot,dm-pre-reloc;
284 	u-boot,dm-pre-reloc;
288 	u-boot,dm-pre-reloc;
292 	u-boot,dm-pre-reloc;
297 	u-boot,dm-pre-reloc;
301 	u-boot,dm-pre-reloc;
305 	u-boot,dm-pre-reloc;
309 	u-boot,dm-pre-reloc;
313 	u-boot,dm-pre-reloc;
318 	u-boot,dm-spl;
319 	/delete-property/ pinctrl-names;
320 	/delete-property/ pinctrl-0;
321 	/delete-property/ assigned-clocks;
322 	/delete-property/ assigned-clock-rates;
325 	#address-cells = <1>;
326 	#size-cells = <0>;
328 		u-boot,dm-spl;
329 		compatible = "spi-nand";
331 		spi-tx-bus-width = <1>;
332 		spi-rx-bus-width = <4>;
333 		spi-max-frequency = <96000000>;
338 	u-boot,dm-spl;