Lines Matching +full:pwm +full:- +full:names
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3562-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/rk3562-power.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/soc/rockchip-system-status.h>
14 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
64 compatible = "simple-bus";
65 #address-cells = <2>;
66 #size-cells = <2>;
70 compatible = "fixed-clock";
71 #clock-cells = <0>;
72 clock-frequency = <32768>;
73 clock-output-names = "xin32k";
77 compatible = "fixed-clock";
78 #clock-cells = <0>;
79 clock-frequency = <24000000>;
80 clock-output-names = "xin24m";
84 compatible = "rockchip,rk3562-clock-gate-link";
86 clock-names = "link";
88 #power-domain-cells = <1>;
89 #clock-cells = <0>;
93 compatible = "rockchip,rk3562-clock-gate-link";
95 clock-names = "link";
97 #power-domain-cells = <1>;
98 #clock-cells = <0>;
102 compatible = "rockchip,rk3562-clock-gate-link";
104 clock-names = "link";
106 #power-domain-cells = <1>;
107 #clock-cells = <0>;
111 compatible = "rockchip,rk3562-clock-gate-link";
113 clock-names = "link";
115 #power-domain-cells = <1>;
116 #clock-cells = <0>;
120 compatible = "rockchip,rk3562-clock-gate-link";
122 clock-names = "link";
124 #power-domain-cells = <1>;
125 #clock-cells = <0>;
130 #address-cells = <2>;
131 #size-cells = <0>;
135 compatible = "arm,cortex-a53";
137 enable-method = "psci";
139 operating-points-v2 = <&cpu0_opp_table>;
143 compatible = "arm,cortex-a53";
145 enable-method = "psci";
147 operating-points-v2 = <&cpu0_opp_table>;
151 compatible = "arm,cortex-a53";
153 enable-method = "psci";
155 operating-points-v2 = <&cpu0_opp_table>;
159 compatible = "arm,cortex-a53";
161 enable-method = "psci";
163 operating-points-v2 = <&cpu0_opp_table>;
167 cpu0_opp_table: cpu0-opp-table {
168 compatible = "operating-points-v2";
169 opp-shared;
171 nvmem-cells = <&cpu_leakage>;
172 nvmem-cell-names = "leakage";
174 opp-408000000 {
175 opp-hz = /bits/ 64 <408000000>;
176 opp-microvolt = <900000 900000 1100000>;
177 clock-latency-ns = <40000>;
178 opp-suspend;
180 opp-600000000 {
181 opp-hz = /bits/ 64 <600000000>;
182 opp-microvolt = <900000 900000 1100000>;
183 clock-latency-ns = <40000>;
185 opp-816000000 {
186 opp-hz = /bits/ 64 <816000000>;
187 opp-microvolt = <900000 900000 1100000>;
188 clock-latency-ns = <40000>;
190 opp-1008000000 {
191 opp-hz = /bits/ 64 <1008000000>;
192 opp-microvolt = <900000 900000 1100000>;
193 clock-latency-ns = <40000>;
195 opp-1200000000 {
196 opp-hz = /bits/ 64 <1200000000>;
197 opp-microvolt = <900000 900000 1100000>;
198 clock-latency-ns = <40000>;
202 arm-pmu {
203 compatible = "arm,cortex-a53-pmu";
208 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
213 nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>;
214 nvmem-cell-names = "id", "cpu-version", "cpu-code";
218 csi2_dphy0: csi2-dphy0 {
219 compatible = "rockchip,rk3562-csi2-dphy";
225 csi2_dphy1: csi2-dphy1 {
226 compatible = "rockchip,rk3562-csi2-dphy";
232 csi2_dphy2: csi2-dphy2 {
233 compatible = "rockchip,rk3562-csi2-dphy";
239 csi2_dphy3: csi2-dphy3 {
240 compatible = "rockchip,rk3562-csi2-dphy";
246 csi2_dphy4: csi2-dphy4 {
247 compatible = "rockchip,rk3562-csi2-dphy";
253 csi2_dphy5: csi2-dphy5 {
254 compatible = "rockchip,rk3562-csi2-dphy";
259 display_subsystem: display-subsystem {
260 compatible = "rockchip,display-subsystem";
267 compatible = "arm,scmi-smc";
269 arm,smc-id = <0x82000010>;
270 #address-cells = <1>;
271 #size-cells = <0>;
275 #clock-cells = <1>;
280 mpp_srv: mpp-srv {
281 compatible = "rockchip,mpp-service";
282 rockchip,taskqueue-count = <3>;
283 rockchip,resetgroup-count = <3>;
288 compatible = "arm,psci-1.0";
292 rkcif_mipi_lvds: rkcif-mipi-lvds {
293 compatible = "rockchip,rkcif-mipi-lvds";
299 rkcif_mipi_lvds_sditf: rkcif-mipi-lvds-sditf {
300 compatible = "rockchip,rkcif-sditf";
305 rkcif_mipi_lvds_sditf_vir1: rkcif-mipi-lvds-sditf-vir1 {
306 compatible = "rockchip,rkcif-sditf";
311 rkcif_mipi_lvds_sditf_vir2: rkcif-mipi-lvds-sditf-vir2 {
312 compatible = "rockchip,rkcif-sditf";
317 rkcif_mipi_lvds_sditf_vir3: rkcif-mipi-lvds-sditf-vir3 {
318 compatible = "rockchip,rkcif-sditf";
323 rkcif_mipi_lvds1: rkcif-mipi-lvds1 {
324 compatible = "rockchip,rkcif-mipi-lvds";
330 rkcif_mipi_lvds1_sditf: rkcif-mipi-lvds1-sditf {
331 compatible = "rockchip,rkcif-sditf";
336 rkcif_mipi_lvds1_sditf_vir1: rkcif-mipi-lvds1-sditf-vir1 {
337 compatible = "rockchip,rkcif-sditf";
342 rkcif_mipi_lvds1_sditf_vir2: rkcif-mipi-lvds1-sditf-vir2 {
343 compatible = "rockchip,rkcif-sditf";
348 rkcif_mipi_lvds1_sditf_vir3: rkcif-mipi-lvds1-sditf-vir3 {
349 compatible = "rockchip,rkcif-sditf";
354 rkcif_mipi_lvds2: rkcif-mipi-lvds2 {
355 compatible = "rockchip,rkcif-mipi-lvds";
361 rkcif_mipi_lvds2_sditf: rkcif-mipi-lvds2-sditf {
362 compatible = "rockchip,rkcif-sditf";
367 rkcif_mipi_lvds2_sditf_vir1: rkcif-mipi-lvds2-sditf-vir1 {
368 compatible = "rockchip,rkcif-sditf";
373 rkcif_mipi_lvds2_sditf_vir2: rkcif-mipi-lvds2-sditf-vir2 {
374 compatible = "rockchip,rkcif-sditf";
379 rkcif_mipi_lvds2_sditf_vir3: rkcif-mipi-lvds2-sditf-vir3 {
380 compatible = "rockchip,rkcif-sditf";
385 rkcif_mipi_lvds3: rkcif-mipi-lvds3 {
386 compatible = "rockchip,rkcif-mipi-lvds";
392 rkcif_mipi_lvds3_sditf: rkcif-mipi-lvds3-sditf {
393 compatible = "rockchip,rkcif-sditf";
398 rkcif_mipi_lvds3_sditf_vir1: rkcif-mipi-lvds3-sditf-vir1 {
399 compatible = "rockchip,rkcif-sditf";
404 rkcif_mipi_lvds3_sditf_vir2: rkcif-mipi-lvds3-sditf-vir2 {
405 compatible = "rockchip,rkcif-sditf";
410 rkcif_mipi_lvds3_sditf_vir3: rkcif-mipi-lvds3-sditf-vir3 {
411 compatible = "rockchip,rkcif-sditf";
416 rkisp_vir0: rkisp-vir0 {
417 compatible = "rockchip,rkisp-vir";
422 rkisp_vir1: rkisp-vir1 {
423 compatible = "rockchip,rkisp-vir";
428 rkisp_vir2: rkisp-vir2 {
429 compatible = "rockchip,rkisp-vir";
434 rkisp_vir3: rkisp-vir3 {
435 compatible = "rockchip,rkisp-vir";
440 thermal_zones: thermal-zones {
441 soc_thermal: soc-thermal {
442 polling-delay-passive = <20>; /* milliseconds */
443 polling-delay = <1000>; /* milliseconds */
445 thermal-sensors = <&tsadc 0>;
447 soc_crit: soc-crit {
459 compatible = "arm,armv8-timer";
466 scmi_shmem: scmi-shmem@10f000 {
467 compatible = "arm,scmi-shmem";
472 compatible = "rockchip,rk3562-dwc3", "rockchip,rk3399-dwc3";
475 clock-names = "ref", "suspend", "bus", "pipe_clk";
476 #address-cells = <2>;
477 #size-cells = <2>;
487 phy-names = "usb2-phy", "usb3-phy";
489 power-domains = <&power RK3562_PD_PHP>;
491 reset-names = "usb3-otg";
493 snps,dis-u1-entry-quirk;
494 snps,dis-u2-entry-quirk;
495 snps,dis-u2-freeclk-exists-quirk;
496 snps,dis-del-phy-power-chg-quirk;
497 snps,dis-tx-ipgap-linecheck-quirk;
499 quirk-skip-phy-init;
504 gic: interrupt-controller@fe901000 {
505 compatible = "arm,gic-400";
506 #interrupt-cells = <3>;
507 #address-cells = <0>;
508 interrupt-controller;
517 compatible = "generic-ehci";
522 clock-names = "usbhost", "arbiter", "utmi";
524 phy-names = "usb2-phy";
529 compatible = "generic-ohci";
534 clock-names = "usbhost", "arbiter", "utmi";
536 phy-names = "usb2-phy";
686 compatible = "rockchip,rk3562-pmu-grf", "syscon", "simple-mfd";
689 reboot_mode: reboot-mode {
690 compatible = "syscon-reboot-mode";
692 mode-bootloader = <BOOT_BL_DOWNLOAD>;
693 mode-charge = <BOOT_CHARGING>;
694 mode-fastboot = <BOOT_FASTBOOT>;
695 mode-loader = <BOOT_BL_DOWNLOAD>;
696 mode-normal = <BOOT_NORMAL>;
697 mode-recovery = <BOOT_RECOVERY>;
698 mode-ums = <BOOT_UMS>;
699 mode-panic = <BOOT_PANIC>;
700 mode-watchdog = <BOOT_WATCHDOG>;
705 compatible = "rockchip,rk3562-sys-grf", "syscon", "simple-mfd";
709 compatible = "rockchip,rk3562-lvds";
711 phy-names = "phy";
715 #address-cells = <1>;
716 #size-cells = <0>;
720 #address-cells = <1>;
721 #size-cells = <0>;
725 remote-endpoint = <&vp0_out_lvds>;
731 remote-endpoint = <&vp1_out_lvds>;
739 compatible = "rockchip,rk3562-rgb";
740 pinctrl-names = "default";
741 pinctrl-0 = <&vo_pins>;
745 #address-cells = <1>;
746 #size-cells = <0>;
750 #address-cells = <1>;
751 #size-cells = <0>;
755 remote-endpoint = <&vp0_out_rgb>;
761 remote-endpoint = <&vp1_out_rgb>;
770 compatible = "rockchip,rk3562-peri-grf", "syscon";
775 compatible = "rockchip,rk3562-ioc-grf", "syscon";
780 compatible = "rockchip,rk3562-usbphy-grf", "syscon";
785 compatible = "rockchip,rk3562-pipephy-grf", "syscon";
789 cru: clock-controller@ff100000 {
790 compatible = "rockchip,rk3562-cru";
793 #clock-cells = <1>;
794 #reset-cells = <1>;
796 assigned-clocks =
799 assigned-clock-rates =
805 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c";
808 clock-names = "i2c", "pclk";
810 pinctrl-names = "default";
811 pinctrl-0 = <&i2c0_xfer>;
812 #address-cells = <1>;
813 #size-cells = <0>;
818 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
822 clock-names = "baudclk", "apb_pclk";
823 reg-shift = <2>;
824 reg-io-width = <4>;
830 compatible = "rockchip,rk3066-spi";
833 #address-cells = <1>;
834 #size-cells = <0>;
836 clock-names = "spiclk", "apb_pclk", "sclk_in";
838 dma-names = "tx", "rx";
839 pinctrl-names = "default";
840 pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>;
841 num-cs = <2>;
845 pwm0: pwm@ff230000 {
846 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
848 #pwm-cells = <3>;
849 pinctrl-names = "active";
850 pinctrl-0 = <&pwm0m0_pins>;
852 clock-names = "pwm", "pclk";
856 pwm1: pwm@ff230010 {
857 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
859 #pwm-cells = <3>;
860 pinctrl-names = "active";
861 pinctrl-0 = <&pwm1m0_pins>;
863 clock-names = "pwm", "pclk";
867 pwm2: pwm@ff230020 {
868 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
870 #pwm-cells = <3>;
871 pinctrl-names = "active";
872 pinctrl-0 = <&pwm2m0_pins>;
874 clock-names = "pwm", "pclk";
878 pwm3: pwm@ff230030 {
879 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
883 #pwm-cells = <3>;
884 pinctrl-names = "active";
885 pinctrl-0 = <&pwm3m0_pins>;
887 clock-names = "pwm", "pclk";
891 pmu: power-management@ff258000 {
892 compatible = "rockchip,rk3562-pmu", "syscon", "simple-mfd";
895 power: power-controller {
896 compatible = "rockchip,rk3562-power-controller";
897 #power-domain-cells = <1>;
898 #address-cells = <1>;
899 #size-cells = <0>;
919 #address-cells = <1>;
920 #size-cells = <0>;
931 #address-cells = <1>;
932 #size-cells = <0>;
951 compatible = "rockchip,rk3562-mailbox",
952 "rockchip,rk3368-mailbox";
956 clock-names = "pclk_mailbox";
957 #mbox-cells = <1>;
962 compatible = "rockchip,rk3562-rknpu";
966 clock-names = "aclk", "hclk";
967 assigned-clocks = <&cru ACLK_RKNN>;
968 assigned-clock-rates = <600000000>;
970 reset-names = "srst_a", "srst_h";
971 power-domains = <&power RK3562_PD_NPU>;
977 compatible = "rockchip,iommu-v2";
980 interrupt-names = "rknpu_mmu";
982 clock-names = "aclk", "iface";
983 power-domains = <&power RK3562_PD_NPU>;
984 #iommu-cells = <0>;
989 compatible = "arm,mali-bifrost";
995 interrupt-names = "GPU", "MMU", "JOB";
1001 clock-names = "clk_gpu", "clk_gpu_brg";
1002 power-domains = <&power RK3562_PD_GPU>;
1003 operating-points-v2 = <&gpu_opp_table>;
1004 #cooling-cells = <2>;
1009 gpu_opp_table: gpu-opp-table {
1010 compatible = "operating-points-v2";
1012 nvmem-cells = <&gpu_leakage>;
1013 nvmem-cell-names = "leakage";
1015 opp-300000000 {
1016 opp-hz = /bits/ 64 <300000000>;
1017 opp-microvolt = <900000 900000 1000000>;
1019 opp-400000000 {
1020 opp-hz = /bits/ 64 <400000000>;
1021 opp-microvolt = <900000 900000 1000000>;
1026 compatible = "rockchip,rkv-decoder-vdpu382", "rockchip,rkv-decoder-v2";
1028 reg-names = "regs", "link";
1030 interrupt-names = "irq_dec";
1032 clock-names = "aclk_vcodec", "hclk_vcodec","clk_hevc_cabac";
1033 rockchip,normal-rates = <198000000>, <0>, <396000000>;
1034 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_RKVDEC_HEVC_CA>;
1035 assigned-clock-rates = <198000000>, <396000000>;
1038 reset-names = "video_a", "video_h", "video_hevc_cabac";
1039 power-domains = <&power RK3562_PD_VDPU>;
1042 rockchip,taskqueue-node = <0>;
1043 rockchip,resetgroup-node = <0>;
1044 rockchip,task-capacity = <16>;
1049 compatible = "rockchip,iommu-v2";
1052 interrupt-names = "rkvdec_mmu";
1054 clock-names = "aclk", "iface";
1055 power-domains = <&power RK3562_PD_VDPU>;
1056 #iommu-cells = <0>;
1061 compatible = "rockchip,rkv-encoder-vepu540c", "rockchip,rkv-encoder-v2";
1064 interrupt-names = "irq_rkvenc";
1066 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
1067 rockchip,normal-rates = <297000000>, <0>, <297000000>;
1070 reset-names = "video_a", "video_h", "video_core";
1071 assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_RKVENC_CORE>;
1072 assigned-clock-rates = <297000000>, <297000000>;
1073 power-domains = <&power RK3562_PD_VEPU>;
1076 rockchip,taskqueue-node = <1>;
1077 rockchip,resetgroup-node = <1>;
1082 compatible = "rockchip,iommu-v2";
1085 interrupt-names = "rkvenc_mmu";
1087 clock-names = "aclk", "iface";
1088 power-domains = <&power RK3562_PD_VEPU>;
1089 #iommu-cells = <0>;
1093 mipi0_csi2: mipi0-csi2@ff380000 {
1094 compatible = "rockchip,rk3562-mipi-csi2";
1096 reg-names = "csihost_regs";
1099 interrupt-names = "csi-intr1", "csi-intr2";
1101 clock-names = "pclk_csi2host";
1103 reset-names = "srst_csihost_p";
1107 mipi1_csi2: mipi1-csi2@ff390000 {
1108 compatible = "rockchip,rk3562-mipi-csi2";
1110 reg-names = "csihost_regs";
1113 interrupt-names = "csi-intr1", "csi-intr2";
1115 clock-names = "pclk_csi2host";
1117 reset-names = "srst_csihost_p";
1121 mipi2_csi2: mipi2-csi2@ff3a0000 {
1122 compatible = "rockchip,rk3562-mipi-csi2";
1124 reg-names = "csihost_regs";
1127 interrupt-names = "csi-intr1", "csi-intr2";
1129 clock-names = "pclk_csi2host";
1131 reset-names = "srst_csihost_p";
1135 mipi3_csi2: mipi3-csi2@ff3b0000 {
1136 compatible = "rockchip,rk3562-mipi-csi2";
1138 reg-names = "csihost_regs";
1141 interrupt-names = "csi-intr1", "csi-intr2";
1143 clock-names = "pclk_csi2host";
1145 reset-names = "srst_csihost_p";
1149 csi2_dphy0_hw: csi2-dphy0-hw@ff3c0000 {
1150 compatible = "rockchip,rk3562-csi2-dphy-hw";
1153 clock-names = "pclk";
1155 reset-names = "srst_p_csiphy0";
1160 csi2_dphy1_hw: csi2-dphy1-hw@ff3d0000 {
1161 compatible = "rockchip,rk3562-csi2-dphy-hw";
1164 clock-names = "pclk";
1166 reset-names = "srst_p_csiphy1";
1172 compatible = "rockchip,rk3562-cif";
1174 reg-names = "cif_regs";
1176 interrupt-names = "cif-intr";
1178 clock-names = "aclk_cif", "hclk_cif", "dclk_cif";
1182 reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_d",
1185 power-domains = <&power RK3562_PD_VI>;
1192 compatible = "rockchip,iommu-v2";
1195 interrupt-names = "cif_mmu";
1197 clock-names = "aclk", "iface";
1198 power-domains = <&power RK3562_PD_VI>;
1199 rockchip,disable-mmu-reset;
1200 #iommu-cells = <0>;
1205 compatible = "rockchip,rk3562-rkisp";
1210 interrupt-names = "mipi_irq", "mi_irq", "isp_irq";
1212 clock-names = "aclk_isp", "hclk_isp", "clk_isp_core";
1213 power-domains = <&power RK3562_PD_VI>;
1219 compatible = "rockchip,iommu-v2";
1222 interrupt-names = "isp_mmu";
1224 clock-names = "aclk", "iface";
1225 rockchip,disable-mmu-reset;
1226 #iommu-cells = <0>;
1227 power-domains = <&power RK3562_PD_VI>;
1232 compatible = "rockchip,rk3562-vop";
1234 reg-names = "regs", "gamma_lut";
1240 clock-names = "aclk_vop",
1248 reset-names = "axi",
1253 power-domains = <&power RK3562_PD_VO>;
1258 #address-cells = <1>;
1259 #size-cells = <0>;
1262 #address-cells = <1>;
1263 #size-cells = <0>;
1268 remote-endpoint = <&rgb_in_vp0>;
1273 remote-endpoint = <&dsi_in_vp0>;
1278 remote-endpoint = <&lvds_in_vp0>;
1283 #address-cells = <1>;
1284 #size-cells = <0>;
1289 remote-endpoint = <&rgb_in_vp1>;
1294 remote-endpoint = <&dsi_in_vp1>;
1299 remote-endpoint = <&lvds_in_vp1>;
1306 compatible = "rockchip,iommu-v2";
1309 interrupt-names = "vop_mmu";
1311 clock-names = "aclk", "iface";
1312 #iommu-cells = <0>;
1313 rockchip,disable-device-link-resume;
1314 rockchip,shootdown-entire;
1322 interrupt-names = "rga2_irq";
1324 clock-names = "aclk_rga2", "hclk_rga2", "clk_rga2";
1326 power-domains = <&power RK3562_PD_RGA>;
1331 compatible = "rockchip,iommu-v2";
1334 interrupt-names = "rga2_mmu";
1336 clock-names = "aclk", "iface";
1337 #iommu-cells = <0>;
1338 power-domains = <&power RK3562_PD_RGA>;
1343 compatible = "rockchip,rkv-jpeg-decoder-v1";
1347 clock-names = "aclk_vcodec", "hclk_vcodec";
1348 rockchip,disable-auto-freq;
1350 reset-names = "video_a", "video_h";
1351 power-domains = <&power RK3562_PD_RGA>;
1354 rockchip,taskqueue-node = <2>;
1355 rockchip,resetgroup-node = <2>;
1360 compatible = "rockchip,iommu-v2";
1363 interrupt-names = "jpegd_mmu";
1364 clock-names = "aclk", "iface";
1366 power-domains = <&power RK3562_PD_RGA>;
1367 #iommu-cells = <0>;
1372 compatible = "rockchip,rk3562-pcie", "snps,dw-pcie";
1373 #address-cells = <3>;
1374 #size-cells = <2>;
1375 bus-range = <0x0 0xff>;
1379 clock-names = "aclk_mst", "aclk_slv",
1388 interrupt-names = "msi", "pmc", "sys", "legacy", "msg", "err";
1389 #interrupt-cells = <1>;
1390 interrupt-map-mask = <0 0 0 7>;
1391 interrupt-map = <0 0 0 1 &pcie2x1_intc 0>,
1395 linux,pci-domain = <0>;
1396 num-ib-windows = <8>;
1397 num-viewport = <8>;
1398 num-ob-windows = <2>;
1399 max-link-speed = <2>;
1400 num-lanes = <1>;
1402 phy-names = "pcie-phy";
1409 reg-names = "pcie-dbi", "pcie-apb";
1411 reset-names = "pipe";
1414 pcie2x1_intc: legacy-interrupt-controller {
1415 interrupt-controller;
1416 #address-cells = <0>;
1417 #interrupt-cells = <1>;
1418 interrupt-parent = <&gic>;
1423 compatible = "rockchip,rk3066-spi";
1426 #address-cells = <1>;
1427 #size-cells = <0>;
1429 clock-names = "spiclk", "apb_pclk";
1431 dma-names = "tx", "rx";
1432 pinctrl-names = "default";
1433 pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>;
1434 num-cs = <2>;
1439 compatible = "rockchip,rk3066-spi";
1442 #address-cells = <1>;
1443 #size-cells = <0>;
1445 clock-names = "spiclk", "apb_pclk";
1447 dma-names = "tx", "rx";
1448 pinctrl-names = "default";
1449 pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>;
1450 num-cs = <2>;
1455 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
1459 clock-names = "baudclk", "apb_pclk";
1460 reg-shift = <2>;
1461 reg-io-width = <4>;
1467 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
1471 clock-names = "baudclk", "apb_pclk";
1472 reg-shift = <2>;
1473 reg-io-width = <4>;
1479 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
1483 clock-names = "baudclk", "apb_pclk";
1484 reg-shift = <2>;
1485 reg-io-width = <4>;
1491 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
1495 clock-names = "baudclk", "apb_pclk";
1496 reg-shift = <2>;
1497 reg-io-width = <4>;
1503 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
1507 clock-names = "baudclk", "apb_pclk";
1508 reg-shift = <2>;
1509 reg-io-width = <4>;
1515 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
1519 clock-names = "baudclk", "apb_pclk";
1520 reg-shift = <2>;
1521 reg-io-width = <4>;
1527 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
1531 clock-names = "baudclk", "apb_pclk";
1532 reg-shift = <2>;
1533 reg-io-width = <4>;
1539 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
1543 clock-names = "baudclk", "apb_pclk";
1544 reg-shift = <2>;
1545 reg-io-width = <4>;
1551 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
1555 clock-names = "baudclk", "apb_pclk";
1556 reg-shift = <2>;
1557 reg-io-width = <4>;
1562 pwm4: pwm@ff700000 {
1563 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
1565 #pwm-cells = <3>;
1566 pinctrl-names = "active";
1567 pinctrl-0 = <&pwm4m0_pins>;
1569 clock-names = "pwm", "pclk";
1573 pwm5: pwm@ff700010 {
1574 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
1576 #pwm-cells = <3>;
1577 pinctrl-names = "active";
1578 pinctrl-0 = <&pwm5m0_pins>;
1580 clock-names = "pwm", "pclk";
1584 pwm6: pwm@ff700020 {
1585 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
1587 #pwm-cells = <3>;
1588 pinctrl-names = "active";
1589 pinctrl-0 = <&pwm6m0_pins>;
1591 clock-names = "pwm", "pclk";
1595 pwm7: pwm@ff700030 {
1596 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
1600 #pwm-cells = <3>;
1601 pinctrl-names = "active";
1602 pinctrl-0 = <&pwm7m0_pins>;
1604 clock-names = "pwm", "pclk";
1608 pwm8: pwm@ff710000 {
1609 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
1611 #pwm-cells = <3>;
1612 pinctrl-names = "active";
1613 pinctrl-0 = <&pwm8m0_pins>;
1615 clock-names = "pwm", "pclk";
1619 pwm9: pwm@ff710010 {
1620 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
1622 #pwm-cells = <3>;
1623 pinctrl-names = "active";
1624 pinctrl-0 = <&pwm9m0_pins>;
1626 clock-names = "pwm", "pclk";
1630 pwm10: pwm@ff710020 {
1631 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
1633 #pwm-cells = <3>;
1634 pinctrl-names = "active";
1635 pinctrl-0 = <&pwm10m0_pins>;
1637 clock-names = "pwm", "pclk";
1641 pwm11: pwm@ff710030 {
1642 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
1646 #pwm-cells = <3>;
1647 pinctrl-names = "active";
1648 pinctrl-0 = <&pwm11m0_pins>;
1650 clock-names = "pwm", "pclk";
1654 pwm12: pwm@ff720000 {
1655 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
1657 #pwm-cells = <3>;
1658 pinctrl-names = "active";
1659 pinctrl-0 = <&pwm12m0_pins>;
1661 clock-names = "pwm", "pclk";
1665 pwm13: pwm@ff720010 {
1666 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
1668 #pwm-cells = <3>;
1669 pinctrl-names = "active";
1670 pinctrl-0 = <&pwm13m0_pins>;
1672 clock-names = "pwm", "pclk";
1676 pwm14: pwm@ff720020 {
1677 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
1679 #pwm-cells = <3>;
1680 pinctrl-names = "active";
1681 pinctrl-0 = <&pwm14m0_pins>;
1683 clock-names = "pwm", "pclk";
1687 pwm15: pwm@ff720030 {
1688 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
1692 #pwm-cells = <3>;
1693 pinctrl-names = "active";
1694 pinctrl-0 = <&pwm15m0_pins>;
1696 clock-names = "pwm", "pclk";
1701 compatible = "rockchip,rk3562-saradc";
1704 #io-channel-cells = <1>;
1706 clock-names = "saradc", "apb_pclk";
1708 reset-names = "saradc-apb";
1712 u2phy: usb2-phy@ff740000 {
1713 compatible = "rockchip,rk3562-usb2phy";
1716 clock-names = "phyclk", "pclk";
1717 #clock-cells = <0>;
1718 clock-output-names = "usb480m_phy";
1722 u2phy_otg: otg-port {
1723 #phy-cells = <0>;
1727 interrupt-names = "otg-bvalid", "otg-id", "linestate";
1731 u2phy_host: host-port {
1732 #phy-cells = <0>;
1734 interrupt-names = "linestate";
1740 compatible = "rockchip,rk3562-naneng-combphy";
1742 #phy-cells = <1>;
1745 clock-names = "refclk", "apbclk", "pipe_clk";
1746 assigned-clocks = <&cru CLK_PIPEPHY_REF>;
1747 assigned-clock-rates = <100000000>;
1749 reset-names = "combphy-apb", "combphy";
1750 rockchip,pipe-grf = <&peri_grf>;
1751 rockchip,pipe-phy-grf = <&pipephy_grf>;
1756 compatible = "rockchip,rk3562-sai", "rockchip,sai-v1";
1760 clock-names = "mclk", "hclk";
1762 dma-names = "tx", "rx";
1764 reset-names = "m", "h";
1765 pinctrl-names = "default";
1766 pinctrl-0 = <&i2s0m0_lrck
1773 #sound-dai-cells = <0>;
1778 compatible = "rockchip,rk3562-sai", "rockchip,sai-v1";
1782 clock-names = "mclk", "hclk";
1784 dma-names = "tx", "rx";
1786 reset-names = "m", "h";
1787 pinctrl-names = "default";
1788 pinctrl-0 = <&i2s1m0_lrck
1798 #sound-dai-cells = <0>;
1803 compatible = "rockchip,rk3562-sai", "rockchip,sai-v1";
1807 clock-names = "mclk", "hclk";
1809 dma-names = "tx", "rx";
1811 reset-names = "m", "h";
1812 pinctrl-names = "default";
1813 pinctrl-0 = <&i2s2m0_lrck
1817 #sound-dai-cells = <0>;
1822 compatible = "rockchip,rk3562-pdm", "rockchip,pdm";
1825 clock-names = "pdm_clk", "pdm_hclk";
1827 dma-names = "rx";
1828 pinctrl-names = "default";
1829 pinctrl-0 = <&pdmm0_clk0
1835 #sound-dai-cells = <0>;
1840 compatible = "rockchip,rk3562-spdif", "rockchip,rk3568-spdif";
1844 dma-names = "tx";
1845 clock-names = "mclk", "hclk";
1847 #sound-dai-cells = <0>;
1848 pinctrl-names = "default";
1849 pinctrl-0 = <&spdifm0_pins>;
1853 acdcdig_dsm: codec-digital@ff850000 {
1854 compatible = "rockchip,rk3562-codec-digital", "rockchip,codec-digital-v1";
1857 clock-names = "dac", "pclk";
1859 reset-names = "reset" ;
1861 rockchip,pwm-output-mode;
1862 pinctrl-names = "default";
1863 pinctrl-0 = <&dsm_pins>;
1864 #sound-dai-cells = <0>;
1873 clock-names = "clk_sfc", "hclk_sfc";
1874 assigned-clocks = <&cru SCLK_SFC>;
1875 assigned-clock-rates = <100000000>;
1876 #address-cells = <1>;
1877 #size-cells = <0>;
1882 compatible = "rockchip,rk3562-dwcmshc", "rockchip,rk3528-dwcmshc";
1885 assigned-clocks = <&cru BCLK_EMMC>, <&cru CCLK_EMMC>;
1886 assigned-clock-rates = <200000000>, <200000000>;
1890 clock-names = "core", "bus", "axi", "block", "timer";
1894 reset-names = "core", "bus", "axi", "block", "timer";
1895 max-frequency = <200000000>;
1900 compatible = "rockchip,rk3562-dw-mshc",
1901 "rockchip,rk3288-dw-mshc";
1904 max-frequency = <150000000>;
1907 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1909 reset-names = "reset";
1910 fifo-depth = <0x100>;
1915 compatible = "rockchip,rk3562-dw-mshc",
1916 "rockchip,rk3288-dw-mshc";
1919 max-frequency = <150000000>;
1922 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1924 reset-names = "reset";
1925 fifo-depth = <0x100>;
1930 compatible = "rockchip,crypto-v4";
1936 clock-names = "sclk", "pka", "aclk", "pclk", "pclk";
1937 assigned-clocks = <&scmi_clk CLK_CORE_CRYPTO>, <&scmi_clk CLK_PKA_CRYPTO>;
1938 assigned-clock-rates = <200000000>, <300000000>;
1940 reset-names = "crypto-rst";
1949 clock-names = "hclk_trng";
1951 reset-names = "reset";
1956 compatible = "rockchip,rk3562-otp";
1958 #address-cells = <1>;
1959 #size-cells = <1>;
1963 clock-names = "usr", "sbpi", "apb", "arb", "phy";
1967 reset-names = "usr", "sbpi", "apb", "arb", "phy";
1970 cpu_code: cpu-code@2 {
1973 otp_cpu_version: cpu-version@8 {
1980 cpu_leakage: cpu-leakage@1a {
1983 log_leakage: log-leakage@1b {
1986 npu_leakage: npu-leakage@1c {
1989 gpu_leakage: gpu-leakage@1d {
1994 dmac: dma-controller@ff990000 {
2000 clock-names = "apb_pclk";
2001 #dma-cells = <1>;
2002 arm,pl330-periph-burst;
2008 #hwlock-cells = <1>;
2013 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c";
2016 clock-names = "i2c", "pclk";
2018 pinctrl-names = "default";
2019 pinctrl-0 = <&i2c1m0_xfer>;
2020 #address-cells = <1>;
2021 #size-cells = <0>;
2026 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c";
2029 clock-names = "i2c", "pclk";
2031 pinctrl-names = "default";
2032 pinctrl-0 = <&i2c2m0_xfer>;
2033 #address-cells = <1>;
2034 #size-cells = <0>;
2039 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c";
2042 clock-names = "i2c", "pclk";
2044 pinctrl-names = "default";
2045 pinctrl-0 = <&i2c3m0_xfer>;
2046 #address-cells = <1>;
2047 #size-cells = <0>;
2052 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c";
2055 clock-names = "i2c", "pclk";
2057 pinctrl-names = "default";
2058 pinctrl-0 = <&i2c4m0_xfer>;
2059 #address-cells = <1>;
2060 #size-cells = <0>;
2065 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c";
2068 clock-names = "i2c", "pclk";
2070 pinctrl-names = "default";
2071 pinctrl-0 = <&i2c5m0_xfer>;
2072 #address-cells = <1>;
2073 #size-cells = <0>;
2078 compatible = "snps,dw-wdt";
2081 clock-names = "tclk", "pclk";
2087 compatible = "rockchip,rk3562-tsadc";
2092 clock-names = "tsadc", "tsadc_tsen", "apb_pclk";
2093 assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>;
2094 assigned-clock-rates = <1200000>, <12000000>;
2096 reset-names = "tsadc", "tsadc-apb", "tsadc-phy";
2097 #thermal-sensor-cells = <1>;
2098 rockchip,hw-tshut-temp = <120000>;
2099 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
2100 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
2105 compatible = "rockchip,rk3562-gmac", "snps,dwmac-4.20a";
2109 interrupt-names = "macirq", "eth_wake_irq";
2114 clock-names = "stmmaceth", "clk_mac_ref",
2117 reset-names = "stmmaceth";
2119 snps,mixed-burst;
2122 snps,axi-config = <&gmac0_stmmac_axi_setup>;
2123 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
2124 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
2128 compatible = "snps,dwmac-mdio";
2129 #address-cells = <0x1>;
2130 #size-cells = <0x0>;
2133 gmac0_stmmac_axi_setup: stmmac-axi-config {
2139 gmac0_mtl_rx_setup: rx-queues-config {
2140 snps,rx-queues-to-use = <1>;
2144 gmac0_mtl_tx_setup: tx-queues-config {
2145 snps,tx-queues-to-use = <1>;
2151 compatible = "rockchip,rk3562-saradc";
2154 #io-channel-cells = <1>;
2156 clock-names = "saradc", "apb_pclk";
2158 reset-names = "saradc-apb";
2163 compatible = "rockchip,rk3562-mailbox",
2164 "rockchip,rk3368-mailbox";
2168 clock-names = "pclk_mailbox";
2169 #mbox-cells = <1>;
2174 compatible = "rockchip,rk3562-mipi-dsi";
2178 clock-names = "pclk";
2180 reset-names = "apb";
2182 phy-names = "dphy";
2184 #address-cells = <1>;
2185 #size-cells = <0>;
2189 #address-cells = <1>;
2190 #size-cells = <0>;
2194 #address-cells = <1>;
2195 #size-cells = <0>;
2199 remote-endpoint = <&vp0_out_dsi>;
2205 remote-endpoint = <&vp1_out_dsi>;
2213 compatible = "rockchip,rk3562-dsi-dphy", "rockchip,rk3562-video-phy",
2214 "rockchip,rk3568-dsi-dphy", "rockchip,rk3568-video-phy";
2217 reg-names = "phy", "host";
2220 clock-names = "ref", "pclk", "pclk_host";
2221 #clock-cells = <0>;
2223 reset-names = "apb";
2224 #phy-cells = <0>;
2229 compatible = "rockchip,rk3562-gmac";
2233 interrupt-names = "macirq", "eth_wake_irq";
2238 clock-names = "stmmaceth", "clk_mac_ref",
2241 reset-names = "stmmaceth";
2245 compatible = "snps,dwmac-mdio";
2246 #address-cells = <0x1>;
2247 #size-cells = <0x0>;
2252 compatible = "rockchip,rk3562-pinctrl";
2254 #address-cells = <2>;
2255 #size-cells = <2>;
2259 compatible = "rockchip,gpio-bank";
2264 gpio-controller;
2265 #gpio-cells = <2>;
2266 gpio-ranges = <&pinctrl 0 0 32>;
2267 interrupt-controller;
2268 #interrupt-cells = <2>;
2272 compatible = "rockchip,gpio-bank";
2277 gpio-controller;
2278 #gpio-cells = <2>;
2279 gpio-ranges = <&pinctrl 0 32 32>;
2280 interrupt-controller;
2281 #interrupt-cells = <2>;
2285 compatible = "rockchip,gpio-bank";
2290 gpio-controller;
2291 #gpio-cells = <2>;
2292 gpio-ranges = <&pinctrl 0 64 32>;
2293 interrupt-controller;
2294 #interrupt-cells = <2>;
2298 compatible = "rockchip,gpio-bank";
2303 gpio-controller;
2304 #gpio-cells = <2>;
2305 gpio-ranges = <&pinctrl 0 96 32>;
2306 interrupt-controller;
2307 #interrupt-cells = <2>;
2311 compatible = "rockchip,gpio-bank";
2316 gpio-controller;
2317 #gpio-cells = <2>;
2318 gpio-ranges = <&pinctrl 0 128 32>;
2319 interrupt-controller;
2320 #interrupt-cells = <2>;
2325 #include "rk3562-pinctrl.dtsi"