Lines Matching +full:0 +full:xffa30000
71 #clock-cells = <0>;
78 #clock-cells = <0>;
85 reg = <0 0xff100324 0 0x10>;
89 #clock-cells = <0>;
94 reg = <0 0xff100328 0 0x10>;
98 #clock-cells = <0>;
103 reg = <0 0xff10032c 0 0x10>;
107 #clock-cells = <0>;
112 reg = <0 0xff100334 0 0x10>;
116 #clock-cells = <0>;
121 reg = <0 0xff100338 0 0x10>;
125 #clock-cells = <0>;
131 #size-cells = <0>;
133 cpu0: cpu@0 {
136 reg = <0x0 0x0>;
144 reg = <0x0 0x1>;
152 reg = <0x0 0x2>;
160 reg = <0x0 0x3>;
269 arm,smc-id = <0x82000010>;
271 #size-cells = <0>;
274 reg = <0x14>;
445 thermal-sensors = <&tsadc 0>;
468 reg = <0x0 0x0010f000 0x0 0x100>;
483 reg = <0x0 0xfe500000 0x0 0x400000>;
507 #address-cells = <0>;
509 reg = <0x0 0xfe901000 0 0x1000>,
510 <0x0 0xfe902000 0 0x2000>,
511 <0x0 0xfe904000 0 0x2000>,
512 <0x0 0xfe906000 0 0x2000>;
518 reg = <0x0 0xfed00000 0x0 0x40000>;
530 reg = <0x0 0xfed40000 0x0 0x40000>;
542 reg = <0x0 0xfee03800 0x0 0x20>;
547 reg = <0x0 0xfee10000 0x0 0x20>;
552 reg = <0x0 0xfee10100 0x0 0x20>;
557 reg = <0x0 0xfee10200 0x0 0x20>;
562 reg = <0x0 0xfee10300 0x0 0x20>;
567 reg = <0x0 0xfee10400 0x0 0x20>;
572 reg = <0x0 0xfee20000 0x0 0x20>;
577 reg = <0x0 0xfee20100 0x0 0x20>;
582 reg = <0x0 0xfee30000 0x0 0x20>;
587 reg = <0x0 0xfee40000 0x0 0x20>;
592 reg = <0x0 0xfee50000 0x0 0x20>;
597 reg = <0x0 0xfee60000 0x0 0x20>;
602 reg = <0x0 0xfee70000 0x0 0x20>;
607 reg = <0x0 0xfee70100 0x0 0x20>;
612 reg = <0x0 0xfee80000 0x0 0x20>;
617 reg = <0x0 0xfee90000 0x0 0x20>;
622 reg = <0x0 0xfee90100 0x0 0x20>;
627 reg = <0x0 0xfee90200 0x0 0x20>;
632 reg = <0x0 0xfeea0000 0x0 0x20>;
637 reg = <0x0 0xfeea0100 0x0 0x20>;
642 reg = <0x0 0xfeeb0000 0x0 0x20>;
647 reg = <0x0 0xfeeb0100 0x0 0x20>;
652 reg = <0x0 0xfeeb0200 0x0 0x20>;
657 reg = <0x0 0xfeeb0300 0x0 0x20>;
662 reg = <0x0 0xfeeb0400 0x0 0x20>;
667 reg = <0x0 0xfeeb0500 0x0 0x20>;
672 reg = <0x0 0xfeeb0600 0x0 0x20>;
677 reg = <0x0 0xfeeb0700 0x0 0x20>;
682 reg = <0x0 0xfeeb0800 0x0 0x20>;
687 reg = <0x0 0xff010000 0x0 0x10000>;
691 offset = <0x200>;
706 reg = <0x0 0xff030000 0x0 0x10000>;
716 #size-cells = <0>;
718 port@0 {
719 reg = <0>;
721 #size-cells = <0>;
723 lvds_in_vp0: endpoint@0 {
724 reg = <0>;
741 pinctrl-0 = <&vo_pins>;
746 #size-cells = <0>;
748 port@0 {
749 reg = <0>;
751 #size-cells = <0>;
753 rgb_in_vp0: endpoint@0 {
754 reg = <0>;
771 reg = <0x0 0xff040000 0x0 0x10000>;
776 reg = <0x0 0xff060000 0x0 0x30000>;
781 reg = <0x0 0xff090000 0x0 0x8000>;
786 reg = <0x0 0xff098000 0x0 0x8000>;
791 reg = <0x0 0xff100000 0x0 0x40000>;
806 reg = <0x0 0xff200000 0x0 0x1000>;
811 pinctrl-0 = <&i2c0_xfer>;
813 #size-cells = <0>;
819 reg = <0x0 0xff210000 0x0 0x100>;
825 dmas = <&dmac 0>;
831 reg = <0x0 0xff220000 0x0 0x1000>;
834 #size-cells = <0>;
840 pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>;
847 reg = <0x0 0xff230000 0x0 0x10>;
850 pinctrl-0 = <&pwm0m0_pins>;
858 reg = <0x0 0xff230010 0x0 0x10>;
861 pinctrl-0 = <&pwm1m0_pins>;
869 reg = <0x0 0xff230020 0x0 0x10>;
872 pinctrl-0 = <&pwm2m0_pins>;
880 reg = <0x0 0xff230030 0x0 0x10>;
885 pinctrl-0 = <&pwm3m0_pins>;
893 reg = <0x0 0xff258000 0x0 0x1000>;
899 #size-cells = <0>;
920 #size-cells = <0>;
932 #size-cells = <0>;
953 reg = <0x0 0xff290000 0x0 0x200>;
963 reg = <0x0 0xff300000 0x0 0x10000>;
978 reg = <0x0 0xff30b000 0x0 0x40>;
984 #iommu-cells = <0>;
990 reg = <0x0 0xff320000 0x0 0x4000>;
1027 reg = <0x0 0xff340100 0x0 0x400>, <0x0 0xff340000 0x0 0x100>;
1033 rockchip,normal-rates = <198000000>, <0>, <396000000>;
1042 rockchip,taskqueue-node = <0>;
1043 rockchip,resetgroup-node = <0>;
1050 reg = <0x0 0xff340800 0x0 0x40>, <0x0 0xff340900 0x0 0x40>;
1056 #iommu-cells = <0>;
1062 reg = <0x0 0xff360000 0x0 0x6000>;
1067 rockchip,normal-rates = <297000000>, <0>, <297000000>;
1083 reg = <0x0 0xff36f000 0x0 0x40>;
1089 #iommu-cells = <0>;
1095 reg = <0x0 0xff380000 0x0 0x10000>;
1109 reg = <0x0 0xff390000 0x0 0x10000>;
1123 reg = <0x0 0xff3a0000 0x0 0x10000>;
1137 reg = <0x0 0xff3b0000 0x0 0x10000>;
1151 reg = <0x0 0xff3c0000 0x0 0x10000>;
1162 reg = <0x0 0xff3d0000 0x0 0x10000>;
1173 reg = <0x0 0xff3e0000 0x0 0x800>;
1193 reg = <0x0 0xff3e0800 0x0 0x100>;
1200 #iommu-cells = <0>;
1206 reg = <0x0 0xff3f0000 0x0 0x7f00>;
1220 reg = <0x0 0xff3f7f00 0x0 0x100>;
1226 #iommu-cells = <0>;
1233 reg = <0x0 0xff400000 0x0 0x2000>, <0x0 0xff405000 0x0 0x1000>;
1259 #size-cells = <0>;
1261 port@0 {
1263 #size-cells = <0>;
1264 reg = <0>;
1266 vp0_out_rgb: endpoint@0 {
1267 reg = <0>;
1284 #size-cells = <0>;
1287 vp1_out_rgb: endpoint@0 {
1288 reg = <0>;
1307 reg = <0x0 0xff407e00 0x0 0x100>;
1312 #iommu-cells = <0>;
1320 reg = <0x0 0xff440000 0x0 0x1000>;
1332 reg = <0x0 0xff440f00 0x0 0x100>;
1337 #iommu-cells = <0>;
1344 reg = <0x0 0xff450000 0x0 0x400>;
1361 reg = <0x0 0xff450480 0x0 0x40>;
1367 #iommu-cells = <0>;
1375 bus-range = <0x0 0xff>;
1390 interrupt-map-mask = <0 0 0 7>;
1391 interrupt-map = <0 0 0 1 &pcie2x1_intc 0>,
1392 <0 0 0 2 &pcie2x1_intc 1>,
1393 <0 0 0 3 &pcie2x1_intc 2>,
1394 <0 0 0 4 &pcie2x1_intc 3>;
1395 linux,pci-domain = <0>;
1403 ranges = <0x00000800 0x0 0xfc000000 0x0 0xfc000000 0x0 0x100000
1404 0x81000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000
1405 0x82000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000
1406 0xc3000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>;
1407 reg = <0x0 0xfe000000 0x0 0x400000>,
1408 <0x0 0xff500000 0x0 0x10000>;
1416 #address-cells = <0>;
1424 reg = <0x0 0xff640000 0x0 0x1000>;
1427 #size-cells = <0>;
1433 pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>;
1440 reg = <0x0 0xff650000 0x0 0x1000>;
1443 #size-cells = <0>;
1449 pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>;
1456 reg = <0x0 0xff670000 0x0 0x100>;
1468 reg = <0x0 0xff680000 0x0 0x100>;
1480 reg = <0x0 0xff690000 0x0 0x100>;
1492 reg = <0x0 0xff6a0000 0x0 0x100>;
1504 reg = <0x0 0xff6b0000 0x0 0x100>;
1516 reg = <0x0 0xff6c0000 0x0 0x100>;
1528 reg = <0x0 0xff6d0000 0x0 0x100>;
1540 reg = <0x0 0xff6e0000 0x0 0x100>;
1552 reg = <0x0 0xff6f0000 0x0 0x100>;
1564 reg = <0x0 0xff700000 0x0 0x10>;
1567 pinctrl-0 = <&pwm4m0_pins>;
1575 reg = <0x0 0xff700010 0x0 0x10>;
1578 pinctrl-0 = <&pwm5m0_pins>;
1586 reg = <0x0 0xff700020 0x0 0x10>;
1589 pinctrl-0 = <&pwm6m0_pins>;
1597 reg = <0x0 0xff700030 0x0 0x10>;
1602 pinctrl-0 = <&pwm7m0_pins>;
1610 reg = <0x0 0xff710000 0x0 0x10>;
1613 pinctrl-0 = <&pwm8m0_pins>;
1621 reg = <0x0 0xff710010 0x0 0x10>;
1624 pinctrl-0 = <&pwm9m0_pins>;
1632 reg = <0x0 0xff710020 0x0 0x10>;
1635 pinctrl-0 = <&pwm10m0_pins>;
1643 reg = <0x0 0xff710030 0x0 0x10>;
1648 pinctrl-0 = <&pwm11m0_pins>;
1656 reg = <0x0 0xff720000 0x0 0x10>;
1659 pinctrl-0 = <&pwm12m0_pins>;
1667 reg = <0x0 0xff720010 0x0 0x10>;
1670 pinctrl-0 = <&pwm13m0_pins>;
1678 reg = <0x0 0xff720020 0x0 0x10>;
1681 pinctrl-0 = <&pwm14m0_pins>;
1689 reg = <0x0 0xff720030 0x0 0x10>;
1694 pinctrl-0 = <&pwm15m0_pins>;
1702 reg = <0x0 0xff730000 0x0 0x100>;
1714 reg = <0x0 0xff740000 0x0 0x10000>;
1717 #clock-cells = <0>;
1723 #phy-cells = <0>;
1732 #phy-cells = <0>;
1741 reg = <0x0 0xff750000 0x0 0x100>;
1757 reg = <0x0 0xff800000 0x0 0x1000>;
1766 pinctrl-0 = <&i2s0m0_lrck
1773 #sound-dai-cells = <0>;
1779 reg = <0x0 0xff810000 0x0 0x1000>;
1788 pinctrl-0 = <&i2s1m0_lrck
1798 #sound-dai-cells = <0>;
1804 reg = <0x0 0xff820000 0x0 0x1000>;
1813 pinctrl-0 = <&i2s2m0_lrck
1817 #sound-dai-cells = <0>;
1823 reg = <0x0 0xff830000 0x0 0x1000>;
1829 pinctrl-0 = <&pdmm0_clk0
1835 #sound-dai-cells = <0>;
1841 reg = <0x0 0xff840000 0x0 0x1000>;
1847 #sound-dai-cells = <0>;
1849 pinctrl-0 = <&spdifm0_pins>;
1855 reg = <0x0 0xff850000 0x0 0x1000>;
1863 pinctrl-0 = <&dsm_pins>;
1864 #sound-dai-cells = <0>;
1870 reg = <0x0 0xff860000 0x0 0x10000>;
1877 #size-cells = <0>;
1883 reg = <0x0 0xff870000 0x0 0x10000>;
1902 reg = <0x0 0xff880000 0x0 0x10000>;
1910 fifo-depth = <0x100>;
1917 reg = <0x0 0xff890000 0x0 0x10000>;
1925 fifo-depth = <0x100>;
1931 reg = <0x0 0xff8a0000 0x0 0x2000>;
1946 reg = <0x0 0xff8e0000 0x0 0x200>;
1957 reg = <0x0 0xff930000 0x0 0x4000>;
1971 reg = <0x02 0x2>;
1974 reg = <0x08 0x1>;
1978 reg = <0x0a 0x10>;
1981 reg = <0x1a 0x1>;
1984 reg = <0x1b 0x1>;
1987 reg = <0x1c 0x1>;
1990 reg = <0x1d 0x1>;
1996 reg = <0x0 0xff990000 0x0 0x4000>;
2007 reg = <0x0 0xff9e0000 0x0 0x100>;
2014 reg = <0x0 0xffa00000 0x0 0x1000>;
2019 pinctrl-0 = <&i2c1m0_xfer>;
2021 #size-cells = <0>;
2027 reg = <0x0 0xffa10000 0x0 0x1000>;
2032 pinctrl-0 = <&i2c2m0_xfer>;
2034 #size-cells = <0>;
2040 reg = <0x0 0xffa20000 0x0 0x1000>;
2045 pinctrl-0 = <&i2c3m0_xfer>;
2047 #size-cells = <0>;
2053 reg = <0x0 0xffa30000 0x0 0x1000>;
2058 pinctrl-0 = <&i2c4m0_xfer>;
2060 #size-cells = <0>;
2066 reg = <0x0 0xffa40000 0x0 0x1000>;
2071 pinctrl-0 = <&i2c5m0_xfer>;
2073 #size-cells = <0>;
2079 reg = <0x0 0xffa60000 0x0 0x100>;
2088 reg = <0x0 0xffa70000 0x0 0x400>;
2099 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
2100 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
2106 reg = <0x0 0xffa80000 0x0 0x10000>;
2129 #address-cells = <0x1>;
2130 #size-cells = <0x0>;
2136 snps,blen = <0 0 0 0 16 8 4>;
2152 reg = <0x0 0xffaa0000 0x0 0x100>;
2165 reg = <0x0 0xffae0000 0x0 0x200>;
2175 reg = <0x0 0xffb10000 0x0 0x10000>;
2185 #size-cells = <0>;
2190 #size-cells = <0>;
2192 dsi_in: port@0 {
2193 reg = <0>;
2195 #size-cells = <0>;
2197 dsi_in_vp0: endpoint@0 {
2198 reg = <0>;
2215 reg = <0x0 0xffb20000 0x0 0x10000>,
2216 <0x0 0xffb10000 0x0 0x10000>;
2221 #clock-cells = <0>;
2224 #phy-cells = <0>;
2230 reg = <0x0 0xffb30000 0x0 0x10000>;
2246 #address-cells = <0x1>;
2247 #size-cells = <0x0>;
2260 reg = <0x0 0xff260000 0x0 0x100>;
2261 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
2266 gpio-ranges = <&pinctrl 0 0 32>;
2273 reg = <0x0 0xff620000 0x0 0x100>;
2279 gpio-ranges = <&pinctrl 0 32 32>;
2286 reg = <0x0 0xff630000 0x0 0x100>;
2292 gpio-ranges = <&pinctrl 0 64 32>;
2299 reg = <0x0 0xffac0000 0x0 0x100>;
2305 gpio-ranges = <&pinctrl 0 96 32>;
2312 reg = <0x0 0xffad0000 0x0 0x100>;
2318 gpio-ranges = <&pinctrl 0 128 32>;