Lines Matching +full:1 +full:- +full:3
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rockchip-pinconf.dtsi"
15 camm0_pins: camm0-pins {
18 <3 RK_PB2 2 &pcfg_pull_none>,
20 <3 RK_PB3 2 &pcfg_pull_none>;
23 camm1_pins: camm1-pins {
26 <4 RK_PB1 3 &pcfg_pull_none>,
28 <4 RK_PB7 3 &pcfg_pull_none>;
31 cam_clk2_out: cam-clk2-out {
34 <3 RK_PB4 2 &pcfg_pull_none>;
36 cam_clk3_out: cam-clk3-out {
39 <3 RK_PB5 2 &pcfg_pull_none>;
44 can0m0_pins: can0m0-pins {
47 <3 RK_PA1 4 &pcfg_pull_none>,
49 <3 RK_PA0 4 &pcfg_pull_none>;
52 can0m1_pins: can0m1-pins {
55 <3 RK_PB7 6 &pcfg_pull_none>,
57 <3 RK_PB6 6 &pcfg_pull_none>;
60 can0m2_pins: can0m2-pins {
70 can1m0_pins: can1m0-pins {
73 <1 RK_PB7 4 &pcfg_pull_none>,
75 <1 RK_PC0 5 &pcfg_pull_none>;
78 can1m1_pins: can1m1-pins {
88 clk_32k_in: clk-32k-in {
91 <0 RK_PB0 1 &pcfg_pull_none>;
96 clk0_32k_out: clk0-32k-out {
104 clk1_32k_out: clk1-32k-out {
107 <2 RK_PA1 3 &pcfg_pull_none>;
112 cpu_pins: cpu-pins {
115 <0 RK_PB7 3 &pcfg_pull_none>;
120 dsm_pins: dsm-pins {
123 <1 RK_PB4 5 &pcfg_pull_none>,
125 <1 RK_PB3 5 &pcfg_pull_none>,
127 <1 RK_PB6 6 &pcfg_pull_none>,
129 <1 RK_PB5 6 &pcfg_pull_none>;
134 emmc_bus8: emmc-bus8 {
137 <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
139 <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
141 <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
143 <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>,
145 <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
147 <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
149 <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
151 <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
154 emmc_clk: emmc-clk {
157 <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
160 emmc_cmd: emmc-cmd {
163 <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
166 emmc_strb: emmc-strb {
169 <1 RK_PB2 1 &pcfg_pull_none>;
174 ethm0_pins: ethm0-pins {
180 ethm1_pins: ethm1-pins {
188 fspi_pins: fspi-pins {
191 <1 RK_PB1 2 &pcfg_pull_none>,
193 <1 RK_PA0 2 &pcfg_pull_none>,
195 <1 RK_PA1 2 &pcfg_pull_none>,
197 <1 RK_PA2 2 &pcfg_pull_none>,
199 <1 RK_PA3 2 &pcfg_pull_none>;
202 fspi_csn0: fspi-csn0 {
205 <1 RK_PB0 2 &pcfg_pull_none>;
207 fspi_csn1: fspi-csn1 {
210 <1 RK_PB2 2 &pcfg_pull_none>;
215 gpu_pins: gpu-pins {
218 <0 RK_PC0 3 &pcfg_pull_none>;
223 i2c0_xfer: i2c0-xfer {
226 <0 RK_PB1 1 &pcfg_pull_none_smt>,
228 <0 RK_PB2 1 &pcfg_pull_none_smt>;
233 i2c1m0_xfer: i2c1m0-xfer {
236 <0 RK_PB3 1 &pcfg_pull_none_smt>,
238 <0 RK_PB4 1 &pcfg_pull_none_smt>;
241 i2c1m1_xfer: i2c1m1-xfer {
251 i2c2m0_xfer: i2c2m0-xfer {
254 <0 RK_PB5 1 &pcfg_pull_none_smt>,
256 <0 RK_PB6 1 &pcfg_pull_none_smt>;
259 i2c2m1_xfer: i2c2m1-xfer {
262 <3 RK_PD2 5 &pcfg_pull_none_smt>,
264 <3 RK_PD3 5 &pcfg_pull_none_smt>;
269 i2c3m0_xfer: i2c3m0-xfer {
272 <3 RK_PA0 1 &pcfg_pull_none_smt>,
274 <3 RK_PA1 1 &pcfg_pull_none_smt>;
277 i2c3m1_xfer: i2c3m1-xfer {
287 i2c4m0_xfer: i2c4m0-xfer {
290 <3 RK_PB6 5 &pcfg_pull_none_smt>,
292 <3 RK_PB7 5 &pcfg_pull_none_smt>;
295 i2c4m1_xfer: i2c4m1-xfer {
305 i2c5m0_xfer: i2c5m0-xfer {
308 <3 RK_PC2 1 &pcfg_pull_none_smt>,
310 <3 RK_PC3 1 &pcfg_pull_none_smt>;
313 i2c5m1_xfer: i2c5m1-xfer {
316 <1 RK_PC7 4 &pcfg_pull_none_smt>,
318 <1 RK_PD0 4 &pcfg_pull_none_smt>;
323 i2s0m0_lrck: i2s0m0-lrck {
326 <3 RK_PA4 1 &pcfg_pull_none>;
329 i2s0m0_mclk: i2s0m0-mclk {
332 <3 RK_PA2 1 &pcfg_pull_none>;
335 i2s0m0_sclk: i2s0m0-sclk {
338 <3 RK_PA3 1 &pcfg_pull_none>;
341 i2s0m0_sdi0: i2s0m0-sdi0 {
344 <3 RK_PB1 1 &pcfg_pull_none>;
347 i2s0m0_sdi1: i2s0m0-sdi1 {
350 <3 RK_PB0 2 &pcfg_pull_none>;
353 i2s0m0_sdi2: i2s0m0-sdi2 {
356 <3 RK_PA7 2 &pcfg_pull_none>;
359 i2s0m0_sdi3: i2s0m0-sdi3 {
362 <3 RK_PA6 2 &pcfg_pull_none>;
365 i2s0m0_sdo0: i2s0m0-sdo0 {
368 <3 RK_PA5 1 &pcfg_pull_none>;
371 i2s0m0_sdo1: i2s0m0-sdo1 {
374 <3 RK_PA6 1 &pcfg_pull_none>;
377 i2s0m0_sdo2: i2s0m0-sdo2 {
380 <3 RK_PA7 1 &pcfg_pull_none>;
383 i2s0m0_sdo3: i2s0m0-sdo3 {
386 <3 RK_PB0 1 &pcfg_pull_none>;
389 i2s0m1_lrck: i2s0m1-lrck {
392 <1 RK_PC4 3 &pcfg_pull_none>;
395 i2s0m1_mclk: i2s0m1-mclk {
398 <1 RK_PC6 3 &pcfg_pull_none>;
401 i2s0m1_sclk: i2s0m1-sclk {
404 <1 RK_PC5 3 &pcfg_pull_none>;
407 i2s0m1_sdi0: i2s0m1-sdi0 {
410 <1 RK_PC1 3 &pcfg_pull_none>;
413 i2s0m1_sdi1: i2s0m1-sdi1 {
416 <1 RK_PC2 3 &pcfg_pull_none>;
419 i2s0m1_sdi2: i2s0m1-sdi2 {
422 <1 RK_PD3 3 &pcfg_pull_none>;
425 i2s0m1_sdi3: i2s0m1-sdi3 {
428 <1 RK_PD4 3 &pcfg_pull_none>;
431 i2s0m1_sdo0: i2s0m1-sdo0 {
434 <1 RK_PC3 3 &pcfg_pull_none>;
437 i2s0m1_sdo1: i2s0m1-sdo1 {
440 <1 RK_PD1 3 &pcfg_pull_none>;
443 i2s0m1_sdo2: i2s0m1-sdo2 {
446 <1 RK_PD2 3 &pcfg_pull_none>;
449 i2s0m1_sdo3: i2s0m1-sdo3 {
457 i2s1m0_lrck: i2s1m0-lrck {
460 <3 RK_PC6 2 &pcfg_pull_none>;
463 i2s1m0_mclk: i2s1m0-mclk {
466 <3 RK_PC4 2 &pcfg_pull_none>;
469 i2s1m0_sclk: i2s1m0-sclk {
472 <3 RK_PC5 2 &pcfg_pull_none>;
475 i2s1m0_sdi0: i2s1m0-sdi0 {
478 <3 RK_PD0 2 &pcfg_pull_none>;
481 i2s1m0_sdi1: i2s1m0-sdi1 {
484 <3 RK_PD1 2 &pcfg_pull_none>;
487 i2s1m0_sdi2: i2s1m0-sdi2 {
490 <3 RK_PD2 2 &pcfg_pull_none>;
493 i2s1m0_sdi3: i2s1m0-sdi3 {
496 <3 RK_PD3 2 &pcfg_pull_none>;
499 i2s1m0_sdo0: i2s1m0-sdo0 {
502 <3 RK_PC7 2 &pcfg_pull_none>;
505 i2s1m0_sdo1: i2s1m0-sdo1 {
511 i2s1m0_sdo2: i2s1m0-sdo2 {
517 i2s1m0_sdo3: i2s1m0-sdo3 {
523 i2s1m1_lrck: i2s1m1-lrck {
526 <3 RK_PB4 1 &pcfg_pull_none>;
529 i2s1m1_mclk: i2s1m1-mclk {
532 <3 RK_PB2 1 &pcfg_pull_none>;
535 i2s1m1_sclk: i2s1m1-sclk {
538 <3 RK_PB3 1 &pcfg_pull_none>;
541 i2s1m1_sdi0: i2s1m1-sdi0 {
544 <3 RK_PC1 1 &pcfg_pull_none>;
547 i2s1m1_sdi1: i2s1m1-sdi1 {
550 <3 RK_PC0 2 &pcfg_pull_none>;
553 i2s1m1_sdi2: i2s1m1-sdi2 {
556 <3 RK_PB7 2 &pcfg_pull_none>;
559 i2s1m1_sdi3: i2s1m1-sdi3 {
562 <3 RK_PB6 2 &pcfg_pull_none>;
565 i2s1m1_sdo0: i2s1m1-sdo0 {
568 <3 RK_PB5 1 &pcfg_pull_none>;
571 i2s1m1_sdo1: i2s1m1-sdo1 {
574 <3 RK_PB6 1 &pcfg_pull_none>;
577 i2s1m1_sdo2: i2s1m1-sdo2 {
580 <3 RK_PB7 1 &pcfg_pull_none>;
583 i2s1m1_sdo3: i2s1m1-sdo3 {
586 <3 RK_PC0 1 &pcfg_pull_none>;
591 i2s2m0_lrck: i2s2m0-lrck {
594 <1 RK_PD6 1 &pcfg_pull_none>;
597 i2s2m0_mclk: i2s2m0-mclk {
600 <2 RK_PA1 1 &pcfg_pull_none>;
603 i2s2m0_sclk: i2s2m0-sclk {
606 <1 RK_PD5 1 &pcfg_pull_none>;
609 i2s2m0_sdi: i2s2m0-sdi {
612 <2 RK_PA0 1 &pcfg_pull_none>;
615 i2s2m0_sdo: i2s2m0-sdo {
618 <1 RK_PD7 1 &pcfg_pull_none>;
621 i2s2m1_lrck: i2s2m1-lrck {
624 <4 RK_PA1 3 &pcfg_pull_none>;
627 i2s2m1_mclk: i2s2m1-mclk {
630 <3 RK_PD6 3 &pcfg_pull_none>;
633 i2s2m1_sclk: i2s2m1-sclk {
639 i2s2m1_sdi: i2s2m1-sdi {
642 <3 RK_PD4 4 &pcfg_pull_none>;
645 i2s2m1_sdo: i2s2m1-sdo {
648 <3 RK_PD5 4 &pcfg_pull_none>;
653 isp_pins: isp-pins {
656 <3 RK_PC1 2 &pcfg_pull_none>,
658 <3 RK_PC3 2 &pcfg_pull_none>,
660 <3 RK_PC2 2 &pcfg_pull_none>;
665 jtagm0_pins: jtagm0-pins {
673 jtagm1_pins: jtagm1-pins {
676 <1 RK_PB5 2 &pcfg_pull_none>,
678 <1 RK_PB6 2 &pcfg_pull_none>;
683 npu_pins: npu-pins {
686 <0 RK_PC1 3 &pcfg_pull_none>;
691 pcie20m0_pins: pcie20m0-pins {
694 <0 RK_PA6 1 &pcfg_pull_none>,
701 pcie20m1_pins: pcie20m1-pins {
704 <3 RK_PA6 4 &pcfg_pull_none>,
706 <3 RK_PB0 4 &pcfg_pull_none>,
708 <3 RK_PA7 4 &pcfg_pull_none>;
711 pcie20_buttonrstn: pcie20-buttonrstn {
714 <0 RK_PB0 3 &pcfg_pull_none>;
719 pdmm0_clk0: pdmm0-clk0 {
722 <3 RK_PA6 3 &pcfg_pull_none>;
725 pdmm0_clk1: pdmm0-clk1 {
728 <3 RK_PA2 3 &pcfg_pull_none>;
731 pdmm0_sdi0: pdmm0-sdi0 {
734 <3 RK_PB1 2 &pcfg_pull_none>;
737 pdmm0_sdi1: pdmm0-sdi1 {
740 <3 RK_PB0 3 &pcfg_pull_none>;
743 pdmm0_sdi2: pdmm0-sdi2 {
746 <3 RK_PA7 3 &pcfg_pull_none>;
749 pdmm0_sdi3: pdmm0-sdi3 {
752 <3 RK_PA0 3 &pcfg_pull_none>;
755 pdmm1_clk0: pdmm1-clk0 {
761 pdmm1_clk1: pdmm1-clk1 {
767 pdmm1_sdi0: pdmm1-sdi0 {
773 pdmm1_sdi1: pdmm1-sdi1 {
779 pdmm1_sdi2: pdmm1-sdi2 {
785 pdmm1_sdi3: pdmm1-sdi3 {
793 pmic_int: pmic-int {
798 soc_slppin_gpio: soc-slppin-gpio {
803 soc_slppin_slp: soc-slppin-slp {
805 <0 RK_PA2 1 &pcfg_pull_none>;
810 pmu_pins: pmu-pins {
813 <0 RK_PA5 3 &pcfg_pull_none>;
818 pwm0m0_pins: pwm0m0-pins {
824 pwm0m1_pins: pwm0m1-pins {
827 <1 RK_PC5 4 &pcfg_pull_none>;
832 pwm1m0_pins: pwm1m0-pins {
838 pwm1m1_pins: pwm1m1-pins {
841 <1 RK_PC6 4 &pcfg_pull_none>;
846 pwm2m0_pins: pwm2m0-pins {
852 pwm2m1_pins: pwm2m1-pins {
855 <1 RK_PC7 3 &pcfg_pull_none>;
860 pwm3m0_pins: pwm3m0-pins {
863 <0 RK_PA7 1 &pcfg_pull_none>;
866 pwm3m1_pins: pwm3m1-pins {
869 <1 RK_PD0 3 &pcfg_pull_none>;
874 pwm4m0_pins: pwm4m0-pins {
880 pwm4m1_pins: pwm4m1-pins {
883 <1 RK_PD1 4 &pcfg_pull_none>;
888 pwm5m0_pins: pwm5m0-pins {
894 pwm5m1_pins: pwm5m1-pins {
897 <1 RK_PD2 4 &pcfg_pull_none>;
902 pwm6m0_pins: pwm6m0-pins {
908 pwm6m1_pins: pwm6m1-pins {
911 <1 RK_PD3 4 &pcfg_pull_none>;
916 pwm7m0_pins: pwm7m0-pins {
922 pwm7m1_pins: pwm7m1-pins {
925 <1 RK_PD4 4 &pcfg_pull_none>;
930 pwm8m0_pins: pwm8m0-pins {
933 <3 RK_PA4 2 &pcfg_pull_none>;
936 pwm8m1_pins: pwm8m1-pins {
939 <1 RK_PC1 4 &pcfg_pull_none>;
944 pwm9m0_pins: pwm9m0-pins {
947 <3 RK_PA5 2 &pcfg_pull_none>;
950 pwm9m1_pins: pwm9m1-pins {
953 <1 RK_PC2 4 &pcfg_pull_none>;
958 pwm10m0_pins: pwm10m0-pins {
961 <1 RK_PB5 5 &pcfg_pull_none>;
964 pwm10m1_pins: pwm10m1-pins {
967 <1 RK_PC3 4 &pcfg_pull_none>;
972 pwm11m0_pins: pwm11m0-pins {
975 <1 RK_PB6 5 &pcfg_pull_none>;
978 pwm11m1_pins: pwm11m1-pins {
981 <1 RK_PC4 4 &pcfg_pull_none>;
986 pwm12m0_pins: pwm12m0-pins {
992 pwm12m1_pins: pwm12m1-pins {
995 <3 RK_PB4 5 &pcfg_pull_none>;
1000 pwm13m0_pins: pwm13m0-pins {
1003 <4 RK_PA4 3 &pcfg_pull_none>;
1006 pwm13m1_pins: pwm13m1-pins {
1009 <3 RK_PB5 5 &pcfg_pull_none>;
1014 pwm14m0_pins: pwm14m0-pins {
1017 <3 RK_PC5 4 &pcfg_pull_none>;
1020 pwm14m1_pins: pwm14m1-pins {
1023 <1 RK_PD7 5 &pcfg_pull_none>;
1028 pwm15m0_pins: pwm15m0-pins {
1031 <3 RK_PC6 4 &pcfg_pull_none>;
1034 pwm15m1_pins: pwm15m1-pins {
1042 pwr_pins: pwr-pins {
1045 <0 RK_PA2 1 &pcfg_pull_none>,
1047 <0 RK_PA3 1 &pcfg_pull_none>;
1052 ref_pins: ref-pins {
1055 <0 RK_PA0 1 &pcfg_pull_none>;
1060 rgmiim0_miim: rgmiim0-miim {
1068 rgmiim0_rx_er: rgmiim0-rx_er {
1074 rgmiim0_rx_bus2: rgmiim0-rx_bus2 {
1084 rgmiim0_tx_bus2: rgmiim0-tx_bus2 {
1094 rgmiim0_rgmii_clk: rgmiim0-rgmii_clk {
1099 <3 RK_PD6 2 &pcfg_pull_none>;
1102 rgmiim0_rgmii_bus: rgmiim0-rgmii_bus {
1105 <3 RK_PD7 2 &pcfg_pull_none>,
1109 <3 RK_PD4 2 &pcfg_pull_none>,
1111 <3 RK_PD5 2 &pcfg_pull_none>;
1114 rgmiim0_clk: rgmiim0-clk {
1120 rgmiim1_miim: rgmiim1-miim {
1123 <1 RK_PC7 2 &pcfg_pull_none>,
1125 <1 RK_PD0 2 &pcfg_pull_none>;
1128 rgmiim1_rx_er: rgmiim1-rx_er {
1134 rgmiim1_rx_bus2: rgmiim1-rx_bus2 {
1137 <1 RK_PD4 2 &pcfg_pull_none>,
1139 <1 RK_PD7 2 &pcfg_pull_none>,
1141 <1 RK_PD6 2 &pcfg_pull_none>;
1144 rgmiim1_tx_bus2: rgmiim1-tx_bus2 {
1147 <1 RK_PD1 2 &pcfg_pull_none>,
1149 <1 RK_PD2 2 &pcfg_pull_none>,
1151 <1 RK_PD3 2 &pcfg_pull_none>;
1154 rgmiim1_rgmii_clk: rgmiim1-rgmii_clk {
1157 <1 RK_PC6 2 &pcfg_pull_none>,
1159 <1 RK_PC3 2 &pcfg_pull_none>;
1162 rgmiim1_rgmii_bus: rgmiim1-rgmii_bus {
1165 <1 RK_PC4 2 &pcfg_pull_none>,
1167 <1 RK_PC5 2 &pcfg_pull_none>,
1169 <1 RK_PC1 2 &pcfg_pull_none>,
1171 <1 RK_PC2 2 &pcfg_pull_none>;
1174 rgmiim1_clk: rgmiim1-clk {
1177 <1 RK_PD5 2 &pcfg_pull_none>;
1182 rmii_pins: rmii-pins {
1185 <1 RK_PD5 5 &pcfg_pull_none>,
1187 <1 RK_PC7 5 &pcfg_pull_none>,
1189 <1 RK_PD0 5 &pcfg_pull_none>,
1191 <1 RK_PD4 5 &pcfg_pull_none>,
1193 <1 RK_PD7 6 &pcfg_pull_none>,
1195 <1 RK_PD6 5 &pcfg_pull_none>,
1199 <1 RK_PD1 5 &pcfg_pull_none>,
1201 <1 RK_PD2 5 &pcfg_pull_none>,
1203 <1 RK_PD3 5 &pcfg_pull_none>;
1207 sdmmc0_pins: sdmmc0-pins {
1208 sdmmc0_bus4: sdmmc0-bus4 {
1211 <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>,
1213 <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
1215 <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
1217 <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>;
1220 sdmmc0_clk: sdmmc0-clk {
1223 <1 RK_PC0 1 &pcfg_pull_up_drv_level_2>;
1226 sdmmc0_cmd: sdmmc0-cmd {
1229 <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>;
1232 sdmmc0_det: sdmmc0-det {
1235 <0 RK_PA4 1 &pcfg_pull_up>;
1238 sdmmc0_pwren: sdmmc0-pwren {
1241 <0 RK_PA5 1 &pcfg_pull_none>;
1246 sdmmc1_bus4: sdmmc1-bus4 {
1249 <1 RK_PC1 1 &pcfg_pull_up_drv_level_2>,
1251 <1 RK_PC2 1 &pcfg_pull_up_drv_level_2>,
1253 <1 RK_PC3 1 &pcfg_pull_up_drv_level_2>,
1255 <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>;
1258 sdmmc1_clk: sdmmc1-clk {
1261 <1 RK_PC6 1 &pcfg_pull_up_drv_level_2>;
1264 sdmmc1_cmd: sdmmc1-cmd {
1267 <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>;
1270 sdmmc1_det: sdmmc1-det {
1273 <1 RK_PD0 1 &pcfg_pull_up>;
1276 sdmmc1_pwren: sdmmc1-pwren {
1279 <1 RK_PC7 1 &pcfg_pull_none>;
1284 spdifm0_pins: spdifm0-pins {
1287 <3 RK_PA1 3 &pcfg_pull_none>;
1290 spdifm1_pins: spdifm1-pins {
1296 spdifm2_pins: spdifm2-pins {
1299 <1 RK_PB7 2 &pcfg_pull_none>;
1304 spi0m0_pins: spi0m0-pins {
1307 <0 RK_PC3 3 &pcfg_pull_none>,
1309 <0 RK_PC5 3 &pcfg_pull_none>,
1311 <0 RK_PC4 3 &pcfg_pull_none>;
1314 spi0m0_csn0: spi0m0-csn0 {
1317 <0 RK_PC2 3 &pcfg_pull_none>;
1319 spi0m0_csn1: spi0m0-csn1 {
1322 <0 RK_PB7 1 &pcfg_pull_none>;
1325 spi0m1_pins: spi0m1-pins {
1328 <3 RK_PB5 4 &pcfg_pull_none>,
1330 <3 RK_PC0 4 &pcfg_pull_none>,
1332 <3 RK_PB4 4 &pcfg_pull_none>;
1335 spi0m1_csn0: spi0m1-csn0 {
1338 <3 RK_PB7 4 &pcfg_pull_none>;
1340 spi0m1_csn1: spi0m1-csn1 {
1343 <3 RK_PB6 4 &pcfg_pull_none>;
1348 spi1m0_pins: spi1m0-pins {
1351 <3 RK_PD6 4 &pcfg_pull_none>,
1358 spi1m0_csn0: spi1m0-csn0 {
1361 <3 RK_PD7 4 &pcfg_pull_none>;
1363 spi1m0_csn1: spi1m0-csn1 {
1369 spi1m1_pins: spi1m1-pins {
1372 <1 RK_PC0 4 &pcfg_pull_none>,
1374 <1 RK_PB4 4 &pcfg_pull_none>,
1376 <1 RK_PB3 4 &pcfg_pull_none>;
1379 spi1m1_csn0: spi1m1-csn0 {
1382 <1 RK_PB6 4 &pcfg_pull_none>;
1384 spi1m1_csn1: spi1m1-csn1 {
1387 <1 RK_PB5 4 &pcfg_pull_none>;
1392 spi2m0_pins: spi2m0-pins {
1397 <3 RK_PD2 4 &pcfg_pull_none>,
1399 <3 RK_PD3 4 &pcfg_pull_none>;
1402 spi2m0_csn0: spi2m0-csn0 {
1407 spi2m0_csn1: spi2m0-csn1 {
1413 spi2m1_pins: spi2m1-pins {
1420 <1 RK_PD7 4 &pcfg_pull_none>;
1423 spi2m1_csn0: spi2m1-csn0 {
1426 <1 RK_PD6 4 &pcfg_pull_none>;
1428 spi2m1_csn1: spi2m1-csn1 {
1431 <1 RK_PD5 4 &pcfg_pull_none>;
1436 tsadcm0_pins: tsadcm0-pins {
1439 <0 RK_PA1 1 &pcfg_pull_none>;
1442 tsadcm1_pins: tsadcm1-pins {
1448 tsadc_shut_org: tsadc-shut-org {
1456 uart0m0_xfer: uart0m0-xfer {
1459 <0 RK_PD0 1 &pcfg_pull_up>,
1461 <0 RK_PD1 1 &pcfg_pull_up>;
1464 uart0m1_xfer: uart0m1-xfer {
1467 <1 RK_PB3 2 &pcfg_pull_up>,
1469 <1 RK_PB4 2 &pcfg_pull_up>;
1474 uart1m0_xfer: uart1m0-xfer {
1477 <1 RK_PD1 1 &pcfg_pull_up>,
1479 <1 RK_PD2 1 &pcfg_pull_up>;
1482 uart1m0_ctsn: uart1m0-ctsn {
1485 <1 RK_PD4 1 &pcfg_pull_none>;
1487 uart1m0_rtsn: uart1m0-rtsn {
1490 <1 RK_PD3 1 &pcfg_pull_none>;
1493 uart1m1_xfer: uart1m1-xfer {
1496 <4 RK_PA6 3 &pcfg_pull_up>,
1498 <4 RK_PA5 3 &pcfg_pull_up>;
1501 uart1m1_ctsn: uart1m1-ctsn {
1504 <4 RK_PB0 3 &pcfg_pull_none>;
1506 uart1m1_rtsn: uart1m1-rtsn {
1509 <4 RK_PA7 3 &pcfg_pull_none>;
1514 uart2m0_xfer: uart2m0-xfer {
1517 <0 RK_PC1 1 &pcfg_pull_up>,
1519 <0 RK_PC0 1 &pcfg_pull_up>;
1522 uart2m0_ctsn: uart2m0-ctsn {
1525 <0 RK_PC2 1 &pcfg_pull_none>;
1527 uart2m0_rtsn: uart2m0-rtsn {
1530 <0 RK_PC3 1 &pcfg_pull_none>;
1533 uart2m1_xfer: uart2m1-xfer {
1536 <3 RK_PA1 2 &pcfg_pull_up>,
1538 <3 RK_PA0 2 &pcfg_pull_up>;
1541 uart2m1_ctsn: uart2m1-ctsn {
1544 <3 RK_PA2 2 &pcfg_pull_none>;
1546 uart2m1_rtsn: uart2m1-rtsn {
1549 <3 RK_PA3 2 &pcfg_pull_none>;
1554 uart3m0_xfer: uart3m0-xfer {
1562 uart3m0_ctsn: uart3m0-ctsn {
1565 <4 RK_PB6 3 &pcfg_pull_none>;
1567 uart3m0_rtsn: uart3m0-rtsn {
1570 <3 RK_PD1 4 &pcfg_pull_none>;
1573 uart3m1_xfer: uart3m1-xfer {
1576 <3 RK_PC0 3 &pcfg_pull_up>,
1578 <3 RK_PB7 3 &pcfg_pull_up>;
1581 uart3m1_ctsn: uart3m1-ctsn {
1584 <3 RK_PB6 3 &pcfg_pull_none>;
1586 uart3m1_rtsn: uart3m1-rtsn {
1589 <3 RK_PC1 3 &pcfg_pull_none>;
1594 uart4m0_xfer: uart4m0-xfer {
1597 <3 RK_PD1 3 &pcfg_pull_up>,
1599 <3 RK_PD0 3 &pcfg_pull_up>;
1602 uart4m0_ctsn: uart4m0-ctsn {
1605 <3 RK_PC5 3 &pcfg_pull_none>;
1607 uart4m0_rtsn: uart4m0-rtsn {
1610 <3 RK_PC6 3 &pcfg_pull_none>;
1613 uart4m1_xfer: uart4m1-xfer {
1616 <1 RK_PD5 3 &pcfg_pull_up>,
1618 <1 RK_PD6 3 &pcfg_pull_up>;
1621 uart4m1_ctsn: uart4m1-ctsn {
1624 <2 RK_PA0 3 &pcfg_pull_none>;
1626 uart4m1_rtsn: uart4m1-rtsn {
1629 <1 RK_PD7 3 &pcfg_pull_none>;
1634 uart5m0_xfer: uart5m0-xfer {
1637 <1 RK_PB7 3 &pcfg_pull_up>,
1639 <1 RK_PC0 3 &pcfg_pull_up>;
1642 uart5m0_ctsn: uart5m0-ctsn {
1645 <1 RK_PB5 3 &pcfg_pull_none>;
1647 uart5m0_rtsn: uart5m0-rtsn {
1650 <1 RK_PB6 3 &pcfg_pull_none>;
1653 uart5m1_xfer: uart5m1-xfer {
1656 <3 RK_PA7 5 &pcfg_pull_up>,
1658 <3 RK_PA6 5 &pcfg_pull_up>;
1661 uart5m1_ctsn: uart5m1-ctsn {
1664 <3 RK_PA0 5 &pcfg_pull_none>;
1666 uart5m1_rtsn: uart5m1-rtsn {
1669 <3 RK_PA1 5 &pcfg_pull_none>;
1674 uart6m0_xfer: uart6m0-xfer {
1677 <0 RK_PC7 1 &pcfg_pull_up>,
1679 <0 RK_PC6 1 &pcfg_pull_up>;
1682 uart6m0_ctsn: uart6m0-ctsn {
1685 <0 RK_PC4 1 &pcfg_pull_none>;
1687 uart6m0_rtsn: uart6m0-rtsn {
1690 <0 RK_PC5 1 &pcfg_pull_none>;
1693 uart6m1_xfer: uart6m1-xfer {
1701 uart6m1_ctsn: uart6m1-ctsn {
1704 <4 RK_PA2 3 &pcfg_pull_none>;
1706 uart6m1_rtsn: uart6m1-rtsn {
1709 <4 RK_PA3 3 &pcfg_pull_none>;
1714 uart7m0_xfer: uart7m0-xfer {
1717 <3 RK_PC7 3 &pcfg_pull_up>,
1719 <3 RK_PC4 3 &pcfg_pull_up>;
1722 uart7m0_ctsn: uart7m0-ctsn {
1725 <3 RK_PD2 3 &pcfg_pull_none>;
1727 uart7m0_rtsn: uart7m0-rtsn {
1730 <3 RK_PD3 3 &pcfg_pull_none>;
1733 uart7m1_xfer: uart7m1-xfer {
1736 <1 RK_PB3 3 &pcfg_pull_up>,
1738 <1 RK_PB4 3 &pcfg_pull_up>;
1743 uart8m0_xfer: uart8m0-xfer {
1746 <3 RK_PB3 3 &pcfg_pull_up>,
1748 <3 RK_PB2 3 &pcfg_pull_up>;
1751 uart8m0_ctsn: uart8m0-ctsn {
1754 <3 RK_PB4 3 &pcfg_pull_none>;
1756 uart8m0_rtsn: uart8m0-rtsn {
1759 <3 RK_PB5 3 &pcfg_pull_none>;
1762 uart8m1_xfer: uart8m1-xfer {
1765 <3 RK_PD5 3 &pcfg_pull_up>,
1767 <3 RK_PD4 3 &pcfg_pull_up>;
1770 uart8m1_ctsn: uart8m1-ctsn {
1773 <3 RK_PD7 3 &pcfg_pull_none>;
1775 uart8m1_rtsn: uart8m1-rtsn {
1778 <4 RK_PA0 3 &pcfg_pull_none>;
1783 uart9m0_xfer: uart9m0-xfer {
1786 <4 RK_PB3 3 &pcfg_pull_up>,
1788 <4 RK_PB2 3 &pcfg_pull_up>;
1791 uart9m0_ctsn: uart9m0-ctsn {
1794 <4 RK_PB4 3 &pcfg_pull_none>;
1796 uart9m0_rtsn: uart9m0-rtsn {
1799 <4 RK_PB5 3 &pcfg_pull_none>;
1802 uart9m1_xfer: uart9m1-xfer {
1805 <3 RK_PC3 3 &pcfg_pull_up>,
1807 <3 RK_PC2 3 &pcfg_pull_up>;
1812 vo_pins: vo-pins {
1815 <4 RK_PB7 1 &pcfg_pull_none>,
1817 <4 RK_PA4 1 &pcfg_pull_none>,
1819 <4 RK_PA5 1 &pcfg_pull_none>,
1821 <4 RK_PB2 1 &pcfg_pull_none>,
1823 <3 RK_PC4 1 &pcfg_pull_none>,
1825 <3 RK_PC5 1 &pcfg_pull_none>,
1827 <3 RK_PC6 1 &pcfg_pull_none>,
1829 <3 RK_PC7 1 &pcfg_pull_none>,
1831 <3 RK_PD0 1 &pcfg_pull_none>,
1833 <4 RK_PA6 1 &pcfg_pull_none>,
1835 <4 RK_PA7 1 &pcfg_pull_none>,
1837 <3 RK_PD1 1 &pcfg_pull_none>,
1839 <3 RK_PD2 1 &pcfg_pull_none>,
1841 <3 RK_PD3 1 &pcfg_pull_none>,
1843 <3 RK_PD4 1 &pcfg_pull_none>,
1845 <3 RK_PD5 1 &pcfg_pull_none>,
1847 <3 RK_PD6 1 &pcfg_pull_none>,
1849 <4 RK_PB0 1 &pcfg_pull_none>,
1851 <4 RK_PB1 1 &pcfg_pull_none>,
1853 <4 RK_PB3 1 &pcfg_pull_none>,
1855 <3 RK_PD7 1 &pcfg_pull_none>,
1857 <4 RK_PA0 1 &pcfg_pull_none>,
1859 <4 RK_PA1 1 &pcfg_pull_none>,
1861 <4 RK_PA2 1 &pcfg_pull_none>,
1863 <4 RK_PA3 1 &pcfg_pull_none>,
1865 <4 RK_PB6 1 &pcfg_pull_none>,
1867 <4 RK_PB4 1 &pcfg_pull_none>,
1869 <4 RK_PB5 1 &pcfg_pull_none>;