Lines Matching +full:mixed +full:- +full:burst
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3528-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/phy/phy.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/power/rk3528-power.h>
13 #include <dt-bindings/soc/rockchip,boot-mode.h>
14 #include <dt-bindings/soc/rockchip-system-status.h>
15 #include <dt-bindings/suspend/rockchip-rk3528.h>
16 #include <dt-bindings/thermal/thermal.h>
17 #include <dt-bindings/display/rockchip-tve.h>
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
56 #address-cells = <2>;
57 #size-cells = <0>;
59 cpu-map {
78 compatible = "arm,cortex-a53";
80 enable-method = "psci";
82 operating-points-v2 = <&cpu0_opp_table>;
83 cpu-idle-states = <&CPU_SLEEP0>;
88 compatible = "arm,cortex-a53";
90 enable-method = "psci";
92 operating-points-v2 = <&cpu0_opp_table>;
93 cpu-idle-states = <&CPU_SLEEP0>;
98 compatible = "arm,cortex-a53";
100 enable-method = "psci";
102 operating-points-v2 = <&cpu0_opp_table>;
103 cpu-idle-states = <&CPU_SLEEP1>;
108 compatible = "arm,cortex-a53";
110 enable-method = "psci";
112 operating-points-v2 = <&cpu0_opp_table>;
113 cpu-idle-states = <&CPU_SLEEP1>;
116 idle-states {
117 entry-method = "psci";
119 CPU_SLEEP0: cpu-sleep0 {
120 compatible = "arm,idle-state";
121 local-timer-stop;
122 arm,psci-suspend-param = <0x0010000>;
123 entry-latency-us = <120>;
124 exit-latency-us = <250>;
125 min-residency-us = <900>;
129 CPU_SLEEP1: cpu-sleep {
130 compatible = "arm,idle-state";
131 local-timer-stop;
132 arm,psci-suspend-param = <0x0010000>;
133 entry-latency-us = <120>;
134 exit-latency-us = <250>;
135 min-residency-us = <900>;
141 cpu0_opp_table: cpu0-opp-table {
142 compatible = "operating-points-v2";
143 opp-shared;
145 nvmem-cells = <&cpu_leakage>;
146 nvmem-cell-names = "leakage";
148 rockchip,pvtm-voltage-sel = <
157 rockchip,pvtm-pvtpll;
158 rockchip,pvtm-offset = <0x18>;
159 rockchip,pvtm-sample-time = <1100>;
160 rockchip,pvtm-freq = <1416000>;
161 rockchip,pvtm-volt = <900000>;
162 rockchip,pvtm-ref-temp = <40>;
163 rockchip,pvtm-temp-prop = <0 0>;
164 rockchip,pvtm-thermal-zone = "soc-thermal";
167 opp-408000000 {
168 opp-hz = /bits/ 64 <408000000>;
169 opp-microvolt = <825000 825000 1100000>;
170 clock-latency-ns = <40000>;
171 opp-suspend;
173 opp-600000000 {
174 opp-hz = /bits/ 64 <600000000>;
175 opp-microvolt = <825000 825000 1100000>;
176 clock-latency-ns = <40000>;
178 opp-816000000 {
179 opp-hz = /bits/ 64 <816000000>;
180 opp-microvolt = <825000 825000 1100000>;
181 clock-latency-ns = <40000>;
183 opp-1008000000 {
184 opp-hz = /bits/ 64 <1008000000>;
185 opp-microvolt = <825000 825000 1100000>;
186 clock-latency-ns = <40000>;
188 opp-1200000000 {
189 opp-hz = /bits/ 64 <1200000000>;
190 opp-microvolt = <875000 875000 1100000>;
191 opp-microvolt-L1 = <862500 862500 1100000>;
192 opp-microvolt-L2 = <850000 850000 1100000>;
193 opp-microvolt-L3 = <837500 837500 1100000>;
194 opp-microvolt-L4 = <837500 837500 1100000>;
195 opp-microvolt-L5 = <837500 837500 1100000>;
196 opp-microvolt-L6 = <825000 825000 1100000>;
197 clock-latency-ns = <40000>;
199 opp-1416000000 {
200 opp-hz = /bits/ 64 <1416000000>;
201 opp-microvolt = <937500 937500 1100000>;
202 opp-microvolt-L1 = <925000 925000 1100000>;
203 opp-microvolt-L2 = <912500 912500 1100000>;
204 opp-microvolt-L3 = <900000 900000 1100000>;
205 opp-microvolt-L4 = <900000 900000 1100000>;
206 opp-microvolt-L5 = <900000 900000 1100000>;
207 opp-microvolt-L6 = <887500 887500 1100000>;
208 clock-latency-ns = <40000>;
210 opp-1608000000 {
211 opp-hz = /bits/ 64 <1608000000>;
212 opp-microvolt = <1012500 1012500 1100000>;
213 opp-microvolt-L1 = <1000000 1000000 1100000>;
214 opp-microvolt-L2 = <987500 987500 1100000>;
215 opp-microvolt-L3 = <975000 975000 1100000>;
216 opp-microvolt-L4 = <962500 962500 1100000>;
217 opp-microvolt-L5 = <950000 950000 1100000>;
218 opp-microvolt-L6 = <937500 937500 1100000>;
219 clock-latency-ns = <40000>;
221 opp-1800000000 {
222 opp-hz = /bits/ 64 <1800000000>;
223 opp-microvolt = <1062500 1062500 1100000>;
224 opp-microvolt-L1 = <1050000 1050000 1100000>;
225 opp-microvolt-L2 = <1037500 1037500 1100000>;
226 opp-microvolt-L3 = <1025000 1025000 1100000>;
227 opp-microvolt-L4 = <1012500 1012500 1100000>;
228 opp-microvolt-L5 = <1000000 1000000 1100000>;
229 opp-microvolt-L6 = <987500 987500 1100000>;
230 clock-latency-ns = <40000>;
232 opp-2016000000 {
233 opp-hz = /bits/ 64 <2016000000>;
234 opp-microvolt = <1100000 1100000 1100000>;
235 opp-microvolt-L1 = <1087500 1087500 1100000>;
236 opp-microvolt-L2 = <1075000 1075000 1100000>;
237 opp-microvolt-L3 = <1062500 1062500 1100000>;
238 opp-microvolt-L4 = <1050000 1050000 1100000>;
239 opp-microvolt-L5 = <1037500 1037500 1100000>;
240 opp-microvolt-L6 = <1025000 1025000 1100000>;
241 clock-latency-ns = <40000>;
245 arm-pmu {
246 compatible = "arm,cortex-a53-pmu";
251 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
256 nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>;
257 nvmem-cell-names = "id", "cpu-version", "cpu-code";
260 display_subsystem: display-subsystem {
261 compatible = "rockchip,display-subsystem";
268 compatible = "arm,scmi-smc";
270 arm,smc-id = <0x82000010>;
271 #address-cells = <1>;
272 #size-cells = <0>;
276 #clock-cells = <1>;
281 mpp_srv: mpp-srv {
282 compatible = "rockchip,mpp-service";
283 rockchip,taskqueue-count = <5>;
284 rockchip,resetgroup-count = <5>;
289 compatible = "arm,psci-1.0";
293 rockchip_suspend: rockchip-suspend {
294 compatible = "rockchip,pm-rk3528";
296 rockchip,sleep-debug-en = <0>;
297 rockchip,sleep-mode-config = <
302 rockchip,wakeup-config = <
310 rockchip_system_monitor: rockchip-system-monitor {
311 compatible = "rockchip,system-monitor";
313 rockchip,thermal-zone = "soc-thermal";
316 thermal_zones: thermal-zones {
317 soc_thermal: soc-thermal {
318 polling-delay-passive = <20>; /* milliseconds */
319 polling-delay = <1000>; /* milliseconds */
321 thermal-sensors = <&tsadc 0>;
323 soc_crit: soc-crit {
335 compatible = "arm,armv8-timer";
343 compatible = "fixed-clock";
344 #clock-cells = <0>;
345 clock-frequency = <24000000>;
346 clock-output-names = "xin24m";
349 scmi_shmem: scmi-shmem@10f000 {
350 compatible = "arm,scmi-shmem";
355 compatible = "rockchip,rk3528-pcie", "snps,dw-pcie";
356 #address-cells = <3>;
357 #size-cells = <2>;
358 bus-range = <0x0 0xff>;
363 clock-names = "aclk", "hclk_slv",
374 interrupt-names = "msi", "pmc", "sys", "legacy", "msg", "err";
375 #interrupt-cells = <1>;
376 interrupt-map-mask = <0 0 0 7>;
377 interrupt-map = <0 0 0 1 &pcie2x1_intc 0>,
381 linux,pci-domain = <0>;
382 num-ib-windows = <8>;
383 num-ob-windows = <8>;
384 num-viewport = <4>;
385 max-link-speed = <2>;
386 num-lanes = <1>;
388 phy-names = "pcie-phy";
395 reg-names = "pcie-apb", "pcie-dbi";
398 reset-names = "pcie", "periph", "preset_cru";
401 pcie2x1_intc: legacy-interrupt-controller {
402 interrupt-controller;
403 #address-cells = <0>;
404 #interrupt-cells = <1>;
405 interrupt-parent = <&gic>;
411 compatible = "rockchip,rk3528-dwc3", "rockchip,rk3399-dwc3";
414 clock-names = "ref_clk", "suspend_clk",
416 #address-cells = <2>;
417 #size-cells = <2>;
427 phy-names = "usb2-phy", "usb3-phy";
430 reset-names = "usb3-otg";
432 snps,dis-u1u2-quirk;
433 snps,dis-u2-freeclk-exists-quirk;
434 snps,dis-del-phy-power-chg-quirk;
435 snps,dis-tx-ipgap-linecheck-quirk;
436 snps,xhci-trb-ent-quirk;
438 quirk-skip-phy-init;
443 gic: interrupt-controller@fed01000 {
444 compatible = "arm,gic-400";
445 #interrupt-cells = <3>;
446 #address-cells = <0>;
447 interrupt-controller;
456 compatible = "generic-ehci";
462 clock-names = "usbhost", "arbiter", "utmi";
464 phy-names = "usb2-phy";
469 compatible = "generic-ohci";
475 clock-names = "usbhost", "arbiter", "utmi";
477 phy-names = "usb2-phy";
663 compatible = "rockchip,rk3528-grf", "syscon", "simple-mfd";
666 grf_cru: grf-clock-controller {
667 compatible = "rockchip,rk3528-grf-cru";
668 #clock-cells = <1>;
671 reboot_mode: reboot-mode {
672 compatible = "syscon-reboot-mode";
674 mode-bootloader = <BOOT_BL_DOWNLOAD>;
675 mode-charge = <BOOT_CHARGING>;
676 mode-fastboot = <BOOT_FASTBOOT>;
677 mode-loader = <BOOT_BL_DOWNLOAD>;
678 mode-normal = <BOOT_NORMAL>;
679 mode-recovery = <BOOT_RECOVERY>;
680 mode-ums = <BOOT_UMS>;
681 mode-panic = <BOOT_PANIC>;
682 mode-watchdog = <BOOT_WATCHDOG>;
686 cru: clock-controller@ff4a0000 {
687 compatible = "rockchip,rk3528-cru";
690 #clock-cells = <1>;
691 #reset-cells = <1>;
693 assigned-clocks =
714 assigned-clock-rates =
737 compatible = "rockchip,rk3528-ioc-grf", "syscon";
741 pmu: power-management@ff600000 {
742 compatible = "rockchip,rk3528-pmu", "syscon", "simple-mfd";
745 power: power-controller {
746 compatible = "rockchip,rk3528-power-controller";
747 #power-domain-cells = <1>;
748 #address-cells = <1>;
749 #size-cells = <0>;
777 compatible = "rockchip,rk3528-mailbox",
778 "rockchip,rk3368-mailbox";
782 clock-names = "pclk_mailbox";
783 #mbox-cells = <1>;
788 compatible = "arm,mali-450";
798 interrupt-names = "Mali_GP_IRQ",
807 clock-names = "clk_mali", "aclk_gpu_mali", "pclk_gpu";
808 assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
809 assigned-clock-rates = <300000000>;
810 power-domains = <&power RK3528_PD_GPU>;
811 operating-points-v2 = <&gpu_opp_table>;
815 compatible = "arm,mali-simple-power-model";
818 static-power = <300>;
819 dynamic-power = <396>;
820 ts = <32000 4700 (-80) 2>;
821 thermal-zone = "soc-thermal";
825 gpu_opp_table: gpu-opp-table {
826 compatible = "operating-points-v2";
828 nvmem-cells = <&gpu_leakage>;
829 nvmem-cell-names = "leakage";
831 rockchip,pvtm-voltage-sel = <
839 rockchip,pvtm-pvtpll;
840 rockchip,pvtm-offset = <0x10018>;
841 rockchip,pvtm-sample-time = <1100>;
842 rockchip,pvtm-freq = <700000>;
843 rockchip,pvtm-volt = <900000>;
844 rockchip,pvtm-ref-temp = <40>;
845 rockchip,pvtm-temp-prop = <0 0>;
846 rockchip,pvtm-thermal-zone = "soc-thermal";
849 opp-300000000 {
850 opp-hz = /bits/ 64 <300000000>;
851 opp-microvolt = <825000 825000 1000000>;
853 opp-500000000 {
854 opp-hz = /bits/ 64 <500000000>;
855 opp-microvolt = <825000 825000 1000000>;
857 opp-600000000 {
858 opp-hz = /bits/ 64 <600000000>;
859 opp-microvolt = <825000 825000 1000000>;
861 opp-700000000 {
862 opp-hz = /bits/ 64 <700000000>;
863 opp-microvolt = <825000 825000 1000000>;
864 opp-microvolt-L0 = <850000 850000 1000000>;
865 opp-microvolt-L1 = <837500 837500 1000000>;
866 clock-latency-ns = <40000>;
868 opp-800000000 {
869 opp-hz = /bits/ 64 <800000000>;
870 opp-microvolt = <900000 900000 1000000>;
871 opp-microvolt-L1 = <887500 887500 1000000>;
872 opp-microvolt-L2 = <875000 875000 1000000>;
873 opp-microvolt-L3 = <862500 862500 1000000>;
874 opp-microvolt-L4 = <850000 850000 1000000>;
875 opp-microvolt-L5 = <837500 837500 1000000>;
876 clock-latency-ns = <40000>;
881 compatible = "rockchip,rkv-decoder-v2";
883 reg-names = "regs", "link";
885 interrupt-names = "irq_dec";
887 clock-names = "aclk_vcodec", "hclk_vcodec","clk_hevc_cabac";
888 rockchip,normal-rates = <340000000>, <0>, <600000000>;
889 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>;
890 assigned-clock-rates = <340000000>, <600000000>;
893 reset-names = "video_a", "video_h", "video_hevc_cabac";
894 power-domains = <&power RK3528_PD_RKVDEC>;
897 rockchip,taskqueue-node = <0>;
898 rockchip,resetgroup-node = <0>;
899 rockchip,task-capacity = <16>;
904 compatible = "rockchip,iommu-v2";
907 interrupt-names = "rkvdec_mmu";
909 clock-names = "aclk", "iface", "clk_hevc_cabac";
910 power-domains = <&power RK3528_PD_RKVDEC>;
911 #iommu-cells = <0>;
916 compatible = "rockchip,rkv-encoder-v2";
919 interrupt-names = "irq_rkvenc";
921 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
922 rockchip,normal-rates = <300000000>, <0>, <300000000>;
925 reset-names = "video_a", "video_h", "video_core";
926 assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_CORE_RKVENC>;
927 assigned-clock-rates = <300000000>, <300000000>;
928 power-domains = <&power RK3528_PD_RKVENC>;
931 rockchip,taskqueue-node = <1>;
932 rockchip,resetgroup-node = <1>;
937 compatible = "rockchip,iommu-v2";
940 interrupt-names = "rkvenc_mmu";
942 clock-names = "aclk", "iface";
943 power-domains = <&power RK3528_PD_RKVENC>;
944 #iommu-cells = <0>;
949 compatible = "rockchip,vpu-decoder-v2";
952 interrupt-names = "irq_dec";
954 clock-names = "aclk_vcodec", "hclk_vcodec";
956 reset-names = "shared_video_a", "shared_video_h";
957 power-domains = <&power RK3528_PD_VPU>;
960 rockchip,taskqueue-node = <2>;
961 rockchip,resetgroup-node = <2>;
966 compatible = "rockchip,iommu-v2";
969 interrupt-names = "vdpu_mmu";
970 clock-names = "aclk", "iface";
972 power-domains = <&power RK3528_PD_VPU>;
973 #iommu-cells = <0>;
978 compatible = "rockchip,avs-plus-decoder";
981 interrupt-names = "irq_dec";
983 clock-names = "aclk_vcodec", "hclk_vcodec";
985 reset-names = "shared_video_a", "shared_video_h";
987 power-domains = <&power RK3528_PD_VPU>;
989 rockchip,taskqueue-node = <2>;
990 rockchip,resetgroup-node = <2>;
995 compatible = "rockchip,rk3528-vop";
999 reg-names = "regs",
1007 clock-names = "aclk_vop",
1011 assigned-clocks = <&cru DCLK_VOP0>;
1012 assigned-clock-parents = <&hdmiphy>;
1018 #address-cells = <1>;
1019 #size-cells = <0>;
1022 #address-cells = <1>;
1023 #size-cells = <0>;
1028 remote-endpoint = <&hdmi_in_vp0>;
1033 #address-cells = <1>;
1034 #size-cells = <0>;
1039 remote-endpoint = <&tve_in_vp1>;
1046 compatible = "rockchip,iommu-v2";
1049 interrupt-names = "vop_mmu";
1051 clock-names = "aclk", "iface";
1052 #iommu-cells = <0>;
1053 rockchip,disable-device-link-resume;
1054 rockchip,shootdown-entire;
1062 interrupt-names = "rga2_irq";
1064 clock-names = "aclk_rga2", "hclk_rga2", "clk_rga2";
1070 compatible = "rockchip,iommu-v2";
1073 interrupt-names = "rga2_mmu";
1075 clock-names = "aclk", "iface";
1076 #iommu-cells = <0>;
1081 compatible = "rockchip,iep-v2";
1085 clock-names = "aclk", "hclk", "sclk";
1086 rockchip,normal-rates = <340000000>, <0>, <340000000>;
1087 assigned-clocks = <&cru ACLK_VDPP>, <&cru CLK_CORE_VDPP>;
1088 assigned-clock-rates = <340000000>, <340000000>;
1091 reset-names = "shared_rst_a", "shared_rst_h", "shared_rst_s";
1093 rockchip,taskqueue-node = <3>;
1094 rockchip,resetgroup-node = <3>;
1095 power-domains = <&power RK3528_PD_VO>;
1101 compatible = "rockchip,iommu-v2";
1104 interrupt-names = "iep_mmu";
1106 clock-names = "aclk", "iface";
1107 #iommu-cells = <0>;
1108 power-domains = <&power RK3528_PD_VO>;
1113 compatible = "rockchip,vdpp-v1";
1115 reg-names = "vdpp_regs", "zme_regs";
1118 clock-names = "aclk", "hclk", "sclk";
1119 rockchip,normal-rates = <340000000>, <0>, <340000000>;
1120 assigned-clocks = <&cru ACLK_VDPP>, <&cru CLK_CORE_VDPP>;
1121 assigned-clock-rates = <340000000>, <340000000>;
1124 reset-names = "shared_rst_a", "shared_rst_h", "shared_rst_s";
1126 rockchip,taskqueue-node = <3>;
1127 rockchip,resetgroup-node = <3>;
1128 power-domains = <&power RK3528_PD_VO>;
1134 compatible = "rockchip,rkv-jpeg-decoder-v1";
1138 clock-names = "aclk_vcodec", "hclk_vcodec";
1139 rockchip,disable-auto-freq;
1141 reset-names = "video_a", "video_h";
1142 power-domains = <&power RK3528_PD_VO>;
1145 rockchip,taskqueue-node = <4>;
1146 rockchip,resetgroup-node = <4>;
1151 compatible = "rockchip,iommu-v2";
1154 interrupt-names = "jpegd_mmu";
1155 clock-names = "aclk", "iface";
1157 power-domains = <&power RK3528_PD_VO>;
1158 #iommu-cells = <0>;
1163 compatible = "rockchip,rk3528-tve";
1171 clock-names = "hclk",
1183 rockchip,tve-upsample = <DCLK_UPSAMPLEx4>;
1188 #address-cells = <1>;
1189 #size-cells = <0>;
1193 #address-cells = <1>;
1194 #size-cells = <0>;
1198 remote-endpoint = <&vp1_out_tve>;
1206 compatible = "rockchip,rk3528-hdmi-hdcp2";
1211 clock-names ="aclk_hdcp2", "pclk_hdcp2", "hdcp2_clk_hdmi";
1216 compatible = "rockchip,rk3528-dw-hdmi";
1224 clock-names = "iahb", "isfr", "cec";
1225 reg-io-width = <4>;
1227 pinctrl-names = "default";
1228 pinctrl-0 = <&hdmi_pins>;
1230 phy-names = "hdmi";
1231 #sound-dai-cells = <0>;
1232 hpd-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
1236 #address-cells = <1>;
1237 #size-cells = <0>;
1241 #address-cells = <1>;
1242 #size-cells = <0>;
1246 remote-endpoint = <&vp0_out_hdmi>;
1254 compatible = "rockchip,rk3528-can";
1257 assigned-clocks = <&cru CLK_CAN0>;
1258 assigned-clock-rates = <198000000>;
1260 clock-names = "baudclk", "apb_pclk";
1262 reset-names = "can", "can-apb";
1267 compatible = "rockchip,rk3528-can";
1270 assigned-clocks = <&cru CLK_CAN1>;
1271 assigned-clock-rates = <198000000>;
1273 clock-names = "baudclk", "apb_pclk";
1275 reset-names = "can", "can-apb";
1280 compatible = "rockchip,rk3528-can";
1283 assigned-clocks = <&cru CLK_CAN2>;
1284 assigned-clock-rates = <198000000>;
1286 clock-names = "baudclk", "apb_pclk";
1288 reset-names = "can", "can-apb";
1293 compatible = "rockchip,rk3528-can";
1296 assigned-clocks = <&cru CLK_CAN3>;
1297 assigned-clock-rates = <198000000>;
1299 clock-names = "baudclk", "apb_pclk";
1301 reset-names = "can", "can-apb";
1306 compatible = "rockchip,rk3066-spi";
1309 #address-cells = <1>;
1310 #size-cells = <0>;
1312 clock-names = "spiclk", "apb_pclk";
1314 dma-names = "tx", "rx";
1315 pinctrl-names = "default";
1316 pinctrl-0 = <&spi0_csn0 &spi0_csn1 &spi0_pins>;
1321 compatible = "rockchip,rk3066-spi";
1324 #address-cells = <1>;
1325 #size-cells = <0>;
1327 clock-names = "spiclk", "apb_pclk";
1329 dma-names = "tx", "rx";
1330 pinctrl-names = "default";
1331 pinctrl-0 = <&spi1_csn0 &spi1_csn1 &spi1_pins>;
1336 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
1340 clock-names = "baudclk", "apb_pclk";
1341 reg-shift = <2>;
1342 reg-io-width = <4>;
1348 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
1352 clock-names = "baudclk", "apb_pclk";
1353 reg-shift = <2>;
1354 reg-io-width = <4>;
1360 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
1364 clock-names = "baudclk", "apb_pclk";
1365 reg-shift = <2>;
1366 reg-io-width = <4>;
1372 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
1376 clock-names = "baudclk", "apb_pclk";
1377 reg-shift = <2>;
1378 reg-io-width = <4>;
1384 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
1388 clock-names = "baudclk", "apb_pclk";
1389 reg-shift = <2>;
1390 reg-io-width = <4>;
1396 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
1400 clock-names = "baudclk", "apb_pclk";
1401 reg-shift = <2>;
1402 reg-io-width = <4>;
1408 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
1412 clock-names = "baudclk", "apb_pclk";
1413 reg-shift = <2>;
1414 reg-io-width = <4>;
1420 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
1424 clock-names = "baudclk", "apb_pclk";
1425 reg-shift = <2>;
1426 reg-io-width = <4>;
1432 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
1435 clock-names = "i2c", "pclk";
1437 pinctrl-names = "default";
1438 pinctrl-0 = <&i2c0m0_xfer>;
1439 #address-cells = <1>;
1440 #size-cells = <0>;
1445 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
1448 clock-names = "i2c", "pclk";
1450 pinctrl-names = "default";
1451 pinctrl-0 = <&i2c1m0_xfer>;
1452 #address-cells = <1>;
1453 #size-cells = <0>;
1458 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
1461 clock-names = "i2c", "pclk";
1463 pinctrl-names = "default";
1464 pinctrl-0 = <&i2c2m0_xfer>;
1465 #address-cells = <1>;
1466 #size-cells = <0>;
1471 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
1474 clock-names = "i2c", "pclk";
1476 pinctrl-names = "default";
1477 pinctrl-0 = <&i2c3m0_xfer>;
1478 #address-cells = <1>;
1479 #size-cells = <0>;
1484 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
1487 clock-names = "i2c", "pclk";
1489 pinctrl-names = "default";
1490 pinctrl-0 = <&i2c4_xfer>;
1491 #address-cells = <1>;
1492 #size-cells = <0>;
1497 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
1500 clock-names = "i2c", "pclk";
1502 pinctrl-names = "default";
1503 pinctrl-0 = <&i2c5m0_xfer>;
1504 #address-cells = <1>;
1505 #size-cells = <0>;
1510 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
1513 clock-names = "i2c", "pclk";
1515 pinctrl-names = "default";
1516 pinctrl-0 = <&i2c6m0_xfer>;
1517 #address-cells = <1>;
1518 #size-cells = <0>;
1523 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
1526 clock-names = "i2c", "pclk";
1528 pinctrl-names = "default";
1529 pinctrl-0 = <&i2c7_xfer>;
1530 #address-cells = <1>;
1531 #size-cells = <0>;
1536 compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
1538 #pwm-cells = <3>;
1539 pinctrl-names = "active";
1540 pinctrl-0 = <&pwm0m0_pins>;
1542 clock-names = "pwm", "pclk";
1547 compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
1549 #pwm-cells = <3>;
1550 pinctrl-names = "active";
1551 pinctrl-0 = <&pwm1m0_pins>;
1553 clock-names = "pwm", "pclk";
1558 compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
1560 #pwm-cells = <3>;
1561 pinctrl-names = "active";
1562 pinctrl-0 = <&pwm2m0_pins>;
1564 clock-names = "pwm", "pclk";
1569 compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
1573 #pwm-cells = <3>;
1574 pinctrl-names = "active";
1575 pinctrl-0 = <&pwm3m0_pins>;
1577 clock-names = "pwm", "pclk";
1582 compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
1584 #pwm-cells = <3>;
1585 pinctrl-names = "active";
1586 pinctrl-0 = <&pwm4m0_pins>;
1588 clock-names = "pwm", "pclk";
1593 compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
1595 #pwm-cells = <3>;
1596 pinctrl-names = "active";
1597 pinctrl-0 = <&pwm5m0_pins>;
1599 clock-names = "pwm", "pclk";
1604 compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
1606 #pwm-cells = <3>;
1607 pinctrl-names = "active";
1608 pinctrl-0 = <&pwm6m0_pins>;
1610 clock-names = "pwm", "pclk";
1615 compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
1619 #pwm-cells = <3>;
1620 pinctrl-names = "active";
1621 pinctrl-0 = <&pwm7m0_pins>;
1623 clock-names = "pwm", "pclk";
1628 compatible = "rockchip,rk3528-timer", "rockchip,rk3288-timer";
1632 clock-names = "pclk", "timer";
1636 compatible = "snps,dw-wdt";
1639 clock-names = "tclk", "pclk";
1645 compatible = "rockchip,rk3528-tsadc";
1650 clock-names = "tsadc", "tsadc_tsen", "apb_pclk";
1651 assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>;
1652 assigned-clock-rates = <1200000>, <12000000>;
1654 reset-names = "tsadc", "tsadc-apb";
1655 #thermal-sensor-cells = <1>;
1656 rockchip,hw-tshut-temp = <120000>;
1657 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
1658 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
1663 compatible = "rockchip,rk3528-saradc";
1666 #io-channel-cells = <1>;
1668 clock-names = "saradc", "apb_pclk";
1670 reset-names = "saradc-apb";
1675 compatible = "rockchip,rk3528-sai", "rockchip,sai-v1";
1679 clock-names = "mclk", "hclk";
1681 dma-names = "tx";
1683 reset-names = "m", "h";
1684 #sound-dai-cells = <0>;
1689 compatible = "rockchip,rk3528-sai", "rockchip,sai-v1";
1693 clock-names = "mclk", "hclk";
1695 dma-names = "tx", "rx";
1697 reset-names = "m", "h";
1698 pinctrl-names = "default";
1699 pinctrl-0 = <&i2s0m0_pins>;
1700 #sound-dai-cells = <0>;
1705 compatible = "rockchip,rk3528-sai", "rockchip,sai-v1";
1709 clock-names = "mclk", "hclk";
1711 dma-names = "tx";
1713 reset-names = "m", "h";
1714 #sound-dai-cells = <0>;
1719 compatible = "rockchip,rk3528-sai", "rockchip,sai-v1";
1723 clock-names = "mclk", "hclk";
1725 dma-names = "tx", "rx";
1727 reset-names = "m", "h";
1728 pinctrl-names = "default";
1729 pinctrl-0 = <&i2s1_pins>;
1730 #sound-dai-cells = <0>;
1735 compatible = "rockchip,rk3528-pdm", "rockchip,rk3568-pdm";
1738 clock-names = "pdm_clk", "pdm_hclk";
1740 dma-names = "rx";
1741 pinctrl-names = "default";
1742 pinctrl-0 = <&pdm_clk0
1748 #sound-dai-cells = <0>;
1753 compatible = "rockchip,rk3528-spdif", "rockchip,rk3568-spdif";
1757 dma-names = "tx";
1758 clock-names = "mclk", "hclk";
1760 #sound-dai-cells = <0>;
1761 pinctrl-names = "default";
1762 pinctrl-0 = <&spdifm0_pins>;
1767 compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a";
1771 interrupt-names = "macirq", "eth_wake_irq";
1776 clock-names = "stmmaceth", "clk_mac_ref",
1780 reset-names = "stmmaceth";
1782 snps,mixed-burst;
1785 snps,axi-config = <&gmac0_stmmac_axi_setup>;
1786 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
1787 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
1789 phy-mode = "rmii";
1791 phy-handle = <&rmii0_phy>;
1793 nvmem-cells = <&macphy_bgs>;
1794 nvmem-cell-names = "bgs";
1798 compatible = "snps,dwmac-mdio";
1799 #address-cells = <0x1>;
1800 #size-cells = <0x0>;
1801 rmii0_phy: ethernet-phy@2 {
1802 compatible = "ethernet-phy-id0044.1400", "ethernet-phy-ieee802.3-c22";
1806 phy-is-integrated;
1807 pinctrl-names = "default";
1808 pinctrl-0 = <&fephym0_led_link &fephym0_led_spd>;
1809 nvmem-cells = <&macphy_txlevel>;
1810 nvmem-cell-names = "txlevel";
1814 gmac0_stmmac_axi_setup: stmmac-axi-config {
1820 gmac0_mtl_rx_setup: rx-queues-config {
1821 snps,rx-queues-to-use = <1>;
1825 gmac0_mtl_tx_setup: tx-queues-config {
1826 snps,tx-queues-to-use = <1>;
1832 compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a";
1836 interrupt-names = "macirq", "eth_wake_irq";
1840 clock-names = "stmmaceth", "clk_mac_ref",
1843 reset-names = "stmmaceth";
1845 snps,mixed-burst;
1848 snps,axi-config = <&gmac1_stmmac_axi_setup>;
1849 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
1850 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
1855 compatible = "snps,dwmac-mdio";
1856 #address-cells = <0x1>;
1857 #size-cells = <0x0>;
1860 gmac1_stmmac_axi_setup: stmmac-axi-config {
1866 gmac1_mtl_rx_setup: rx-queues-config {
1867 snps,rx-queues-to-use = <1>;
1871 gmac1_mtl_tx_setup: tx-queues-config {
1872 snps,tx-queues-to-use = <1>;
1878 compatible = "rockchip,rk3528-dwcmshc";
1881 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_SRC_EMMC>;
1882 assigned-clock-rates = <200000000>, <24000000>, <200000000>;
1886 clock-names = "core", "bus", "axi", "block", "timer";
1890 reset-names = "core", "bus", "axi", "block", "timer";
1891 max-frequency = <200000000>;
1900 clock-names = "clk_sfc", "hclk_sfc";
1901 assigned-clocks = <&cru SCLK_SFC>;
1902 assigned-clock-rates = <100000000>;
1903 #address-cells = <1>;
1904 #size-cells = <0>;
1909 compatible = "rockchip,rk3528-dw-mshc",
1910 "rockchip,rk3288-dw-mshc";
1913 max-frequency = <150000000>;
1916 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1917 fifo-depth = <0x100>;
1919 reset-names = "reset";
1920 rockchip,use-v2-tuning;
1925 compatible = "rockchip,rk3528-dw-mshc",
1926 "rockchip,rk3288-dw-mshc";
1929 max-frequency = <150000000>;
1932 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1933 fifo-depth = <0x100>;
1935 reset-names = "reset";
1936 rockchip,use-v2-tuning;
1941 compatible = "rockchip,rk3528-dw-mshc",
1942 "rockchip,rk3288-dw-mshc";
1945 max-frequency = <150000000>;
1948 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1949 fifo-depth = <0x100>;
1951 reset-names = "reset";
1952 rockchip,use-v2-tuning;
1953 pinctrl-names = "default";
1954 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1959 compatible = "rockchip,crypto-v4";
1964 clock-names = "aclk", "hclk", "sclk", "pka";
1965 assigned-clocks = <&scmi_clk SCMI_CORE_CRYPTO>, <&scmi_clk SCMI_PKA_CRYPTO>;
1966 assigned-clock-rates = <300000000>, <300000000>;
1968 reset-names = "crypto-rst";
1977 clock-names = "hclk_trng";
1979 reset-names = "reset";
1984 compatible = "rockchip,rk3528-otp";
1986 #address-cells = <1>;
1987 #size-cells = <1>;
1990 clock-names = "usr", "sbpi", "apb";
1994 reset-names = "usr", "sbpi", "apb";
1997 cpu_code: cpu-code@2 {
2000 otp_cpu_version: cpu-version@8 {
2007 cpu_leakage: cpu-leakage@1a {
2010 log_leakage: log-leakage@1b {
2013 gpu_leakage: gpu-leakage@1c {
2016 macphy_bgs: macphy-bgs@2d {
2019 macphy_txlevel: macphy-txlevel@2e {
2024 dmac: dma-controller@ffd60000 {
2037 clock-names = "apb_pclk";
2038 #dma-cells = <1>;
2039 arm,pl330-periph-burst;
2045 #hwlock-cells = <1>;
2050 compatible = "rockchip,rk3528-naneng-combphy";
2052 #phy-cells = <1>;
2054 clock-names = "refclk", "apbclk", "pipe_clk";
2055 assigned-clocks = <&cru CLK_REF_PCIE_INNER_PHY>;
2056 assigned-clock-rates = <100000000>;
2058 reset-names = "combphy-apb", "combphy";
2059 rockchip,pipe-grf = <&grf>;
2060 rockchip,pipe-phy-grf = <&grf>;
2064 usb2phy: usb2-phy@ffdf0000 {
2065 compatible = "rockchip,rk3528-usb2phy";
2068 clock-names = "phyclk", "apb_pclk";
2069 #clock-cells = <0>;
2073 u2phy_otg: otg-port {
2074 #phy-cells = <0>;
2078 interrupt-names = "otg-bvalid",
2079 "otg-id",
2084 u2phy_host: host-port {
2085 #phy-cells = <0>;
2087 interrupt-names = "linestate";
2093 compatible = "rockchip,rk3528-hdmi-phy";
2096 #phy-cells = <0>;
2098 clock-names = "sysclk", "refclk";
2099 #clock-cells = <0>;
2100 clock-output-names = "clk_hdmiphy_pixel_io";
2105 compatible = "rockchip,rk3528-codec";
2107 #sound-dai-cells = <0>;
2109 clock-names = "pclk", "mclk";
2111 reset-names = "acodec";
2116 compatible = "rockchip,rk3528-pinctrl";
2118 #address-cells = <2>;
2119 #size-cells = <2>;
2123 compatible = "rockchip,gpio-bank";
2127 gpio-controller;
2128 #gpio-cells = <2>;
2129 gpio-ranges = <&pinctrl 0 0 32>;
2130 interrupt-controller;
2131 #interrupt-cells = <2>;
2135 compatible = "rockchip,gpio-bank";
2139 gpio-controller;
2140 #gpio-cells = <2>;
2141 gpio-ranges = <&pinctrl 0 32 32>;
2142 interrupt-controller;
2143 #interrupt-cells = <2>;
2147 compatible = "rockchip,gpio-bank";
2151 gpio-controller;
2152 #gpio-cells = <2>;
2153 gpio-ranges = <&pinctrl 0 64 32>;
2154 interrupt-controller;
2155 #interrupt-cells = <2>;
2159 compatible = "rockchip,gpio-bank";
2163 gpio-controller;
2164 #gpio-cells = <2>;
2165 gpio-ranges = <&pinctrl 0 96 32>;
2166 interrupt-controller;
2167 #interrupt-cells = <2>;
2171 compatible = "rockchip,gpio-bank";
2175 gpio-controller;
2176 #gpio-cells = <2>;
2177 gpio-ranges = <&pinctrl 0 128 32>;
2178 interrupt-controller;
2179 #interrupt-cells = <2>;
2184 #include "rk3528-pinctrl.dtsi"