arm/dts/rk3528-u-boot.dtsi

4  * SPDX-License-Identifier:     GPL-2.0+
14 		stdout-path = &uart2;
15 		u-boot,spl-boot-order = &sdmmc, &sdhci, &spi_nand, &spi_nor;
18 	secure-otp@ffcd0000 {
19 		compatible = "rockchip,rk3528-secure-otp";
24 		u-boot,dm-spl;
31 	u-boot,dm-spl;
36 	u-boot,dm-spl;
41 	/delete-property/ assigned-clocks;
42 	/delete-property/ assigned-clock-rates;
43 	u-boot,dm-spl;
48 	u-boot,dm-spl;
53 	u-boot,dm-pre-reloc;
58 	u-boot,dm-pre-reloc;
63 	clock-frequency = <24000000>;
64 	u-boot,dm-spl;
69 	u-boot,dm-spl;
70 	/delete-property/ pinctrl-names;
71 	/delete-property/ pinctrl-0;
72 	/delete-property/ assigned-clocks;
73 	/delete-property/ assigned-clock-rates;
76 	#address-cells = <1>;
77 	#size-cells = <0>;
79 		u-boot,dm-spl;
80 		compatible = "spi-nand";
82 		spi-tx-bus-width = <1>;
83 		spi-rx-bus-width = <4>;
84 		spi-max-frequency = <75000000>;
88 		u-boot,dm-spl;
89 		compatible = "jedec,spi-nor";
92 		spi-tx-bus-width = <1>;
93 		spi-rx-bus-width = <4>;
94 		spi-max-frequency = <100000000>;
99 	bus-width = <8>;
100 	u-boot,dm-spl;
101 	/delete-property/ assigned-clocks;
102 	/delete-property/ assigned-clock-rates;
103 	/delete-property/ pinctrl-names;
104 	/delete-property/ pinctrl-0;
105 	mmc-hs400-1_8v;
106 	mmc-hs400-enhanced-strobe;
107 	fixed-emmc-driver-type = <1>;
112 	u-boot,dm-spl;
117 	u-boot,dm-pre-reloc;
122 	u-boot,dm-pre-reloc;
127 	u-boot,dm-pre-reloc;
132 	u-boot,dm-spl;
136 	u-boot,dm-spl;
140 	u-boot,dm-spl;
144 	u-boot,dm-spl;
148 	u-boot,dm-spl;
153 	u-boot,dm-spl;
157 	u-boot,dm-spl;
161 	u-boot,dm-spl;
165 	u-boot,dm-spl;
169 	u-boot,dm-spl;
173 	u-boot,dm-spl;
177 	u-boot,dm-spl;
181 	u-boot,dm-spl;
185 	u-boot,dm-spl;
189 	u-boot,dm-spl;
193 	u-boot,dm-spl;
197 	u-boot,dm-spl;
201 	u-boot,dm-spl;
205 	u-boot,dm-spl;