Lines Matching +full:1 +full:- +full:3
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rockchip-pinconf.dtsi"
15 arm_pins: arm-pins {
18 <4 RK_PC4 3 &pcfg_pull_none>;
23 can0m0_pins: can0m0-pins {
26 <4 RK_PA0 3 &pcfg_pull_none>,
28 <4 RK_PA1 3 &pcfg_pull_none>;
31 can0m1_pins: can0m1-pins {
34 <4 RK_PC6 3 &pcfg_pull_none>,
36 <4 RK_PC5 3 &pcfg_pull_none>;
41 can1m0_pins: can1m0-pins {
49 can1m1_pins: can1m1-pins {
59 can2m0_pins: can2m0-pins {
62 <1 RK_PB3 2 &pcfg_pull_none>,
64 <1 RK_PB2 2 &pcfg_pull_none>;
67 can2m1_pins: can2m1-pins {
70 <3 RK_PA5 5 &pcfg_pull_none>,
72 <3 RK_PA4 5 &pcfg_pull_none>;
77 can3m0_pins: can3m0-pins {
80 <1 RK_PB5 2 &pcfg_pull_none>,
82 <1 RK_PB4 2 &pcfg_pull_none>;
85 can3m1_pins: can3m1-pins {
88 <3 RK_PB3 2 &pcfg_pull_none>,
90 <3 RK_PB2 2 &pcfg_pull_none>;
95 clkm0_32k_out: clkm0-32k-out {
98 <3 RK_PC3 3 &pcfg_pull_none>;
101 clkm1_32k_out: clkm1-32k-out {
104 <1 RK_PC3 1 &pcfg_pull_none>;
109 emmc_rstnout: emmc-rstnout {
112 <1 RK_PD6 1 &pcfg_pull_none>;
115 emmc_bus8: emmc-bus8 {
118 <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>,
120 <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>,
122 <1 RK_PC6 1 &pcfg_pull_up_drv_level_2>,
124 <1 RK_PC7 1 &pcfg_pull_up_drv_level_2>,
126 <1 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
128 <1 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
130 <1 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
132 <1 RK_PD3 1 &pcfg_pull_up_drv_level_2>;
135 emmc_clk: emmc-clk {
138 <1 RK_PD5 1 &pcfg_pull_up_drv_level_2>;
141 emmc_cmd: emmc-cmd {
144 <1 RK_PD4 1 &pcfg_pull_up_drv_level_2>;
147 emmc_strb: emmc-strb {
150 <1 RK_PD7 1 &pcfg_pull_none>;
155 eth_pins: eth-pins {
158 <3 RK_PB5 2 &pcfg_pull_none>;
163 fephym0_led_dpx: fephym0-led_dpx {
169 fephym0_led_link: fephym0-led_link {
175 fephym0_led_spd: fephym0-led_spd {
181 fephym1_led_dpx: fephym1-led_dpx {
187 fephym1_led_link: fephym1-led_link {
193 fephym1_led_spd: fephym1-led_spd {
201 fspi_pins: fspi-pins {
204 <1 RK_PD5 2 &pcfg_pull_none>,
206 <1 RK_PC4 2 &pcfg_pull_none>,
208 <1 RK_PC5 2 &pcfg_pull_none>,
210 <1 RK_PC6 2 &pcfg_pull_none>,
212 <1 RK_PC7 2 &pcfg_pull_none>;
215 fspi_csn0: fspi-csn0 {
218 <1 RK_PD0 2 &pcfg_pull_none>;
220 fspi_csn1: fspi-csn1 {
223 <1 RK_PD1 2 &pcfg_pull_none>;
228 gpu_pins: gpu-pins {
231 <4 RK_PC3 3 &pcfg_pull_none>;
236 hdmi_pins: hdmi-pins {
239 <0 RK_PA3 1 &pcfg_pull_none>,
241 <0 RK_PA2 1 &pcfg_pull_none>,
243 <0 RK_PA4 1 &pcfg_pull_none>,
245 <0 RK_PA5 1 &pcfg_pull_none>;
250 hsmm0_pins: hsmm0-pins {
256 hsmm1_pins: hsmm1-pins {
259 <1 RK_PA4 3 &pcfg_pull_none>;
264 i2c0m0_xfer: i2c0m0-xfer {
272 i2c0m1_xfer: i2c0m1-xfer {
282 i2c1m0_xfer: i2c1m0-xfer {
290 i2c1m1_xfer: i2c1m1-xfer {
300 i2c2m0_xfer: i2c2m0-xfer {
308 i2c2m1_xfer: i2c2m1-xfer {
311 <1 RK_PA5 3 &pcfg_pull_none_smt>,
313 <1 RK_PA6 3 &pcfg_pull_none_smt>;
318 i2c3m0_xfer: i2c3m0-xfer {
321 <1 RK_PA0 2 &pcfg_pull_none_smt>,
323 <1 RK_PA1 2 &pcfg_pull_none_smt>;
326 i2c3m1_xfer: i2c3m1-xfer {
329 <3 RK_PC1 5 &pcfg_pull_none_smt>,
331 <3 RK_PC3 5 &pcfg_pull_none_smt>;
336 i2c4_xfer: i2c4-xfer {
346 i2c5m0_xfer: i2c5m0-xfer {
349 <1 RK_PB2 3 &pcfg_pull_none_smt>,
351 <1 RK_PB3 3 &pcfg_pull_none_smt>;
354 i2c5m1_xfer: i2c5m1-xfer {
357 <1 RK_PD2 3 &pcfg_pull_none_smt>,
359 <1 RK_PD3 3 &pcfg_pull_none_smt>;
364 i2c6m0_xfer: i2c6m0-xfer {
367 <3 RK_PB2 5 &pcfg_pull_none_smt>,
369 <3 RK_PB3 5 &pcfg_pull_none_smt>;
372 i2c6m1_xfer: i2c6m1-xfer {
375 <1 RK_PD4 3 &pcfg_pull_none_smt>,
377 <1 RK_PD7 3 &pcfg_pull_none_smt>;
382 i2c7_xfer: i2c7-xfer {
392 i2s0m0_pins: i2s0m0-pins {
395 <3 RK_PB6 1 &pcfg_pull_none>,
397 <3 RK_PB4 1 &pcfg_pull_none>,
399 <3 RK_PB5 1 &pcfg_pull_none>,
401 <3 RK_PB7 1 &pcfg_pull_none>,
403 <3 RK_PC0 1 &pcfg_pull_none>;
406 i2s0m1_pins: i2s0m1-pins {
409 <1 RK_PB6 1 &pcfg_pull_none>,
411 <1 RK_PB4 1 &pcfg_pull_none>,
413 <1 RK_PB5 1 &pcfg_pull_none>,
415 <1 RK_PB7 1 &pcfg_pull_none>,
417 <1 RK_PC0 1 &pcfg_pull_none>;
422 i2s1_pins: i2s1-pins {
425 <4 RK_PA6 1 &pcfg_pull_none>,
427 <4 RK_PA4 1 &pcfg_pull_none>,
429 <4 RK_PA5 1 &pcfg_pull_none>,
431 <4 RK_PB4 1 &pcfg_pull_none>,
433 <4 RK_PB3 1 &pcfg_pull_none>,
435 <4 RK_PA3 1 &pcfg_pull_none>,
437 <4 RK_PA2 1 &pcfg_pull_none>,
439 <4 RK_PA7 1 &pcfg_pull_none>,
441 <4 RK_PB0 1 &pcfg_pull_none>,
443 <4 RK_PB1 1 &pcfg_pull_none>,
445 <4 RK_PB2 1 &pcfg_pull_none>;
450 jtagm0_pins: jtagm0-pins {
462 jtagm1_pins: jtagm1-pins {
469 <4 RK_PD0 3 &pcfg_pull_none>,
471 <4 RK_PC7 3 &pcfg_pull_none>;
476 pciem0_pins: pciem0-pins {
479 <3 RK_PA6 5 &pcfg_pull_none>,
481 <3 RK_PB0 5 &pcfg_pull_none>,
483 <3 RK_PA7 5 &pcfg_pull_none>;
486 pciem1_pins: pciem1-pins {
489 <1 RK_PA0 4 &pcfg_pull_none>,
491 <1 RK_PA2 4 &pcfg_pull_none>,
493 <1 RK_PA1 4 &pcfg_pull_none>;
498 pdm_clk0: pdm-clk0 {
501 <4 RK_PB5 3 &pcfg_pull_none>;
504 pdm_clk1: pdm-clk1 {
507 <4 RK_PA4 3 &pcfg_pull_none>;
510 pdm_sdi0: pdm-sdi0 {
513 <4 RK_PB2 3 &pcfg_pull_none>;
516 pdm_sdi1: pdm-sdi1 {
519 <4 RK_PB1 3 &pcfg_pull_none>;
522 pdm_sdi2: pdm-sdi2 {
525 <4 RK_PB3 3 &pcfg_pull_none>;
528 pdm_sdi3: pdm-sdi3 {
531 <4 RK_PC1 3 &pcfg_pull_none>;
536 pmu_pins: pmu-pins {
544 pwm0m0_pins: pwm0m0-pins {
547 <4 RK_PC3 1 &pcfg_pull_none>;
550 pwm0m1_pins: pwm0m1-pins {
553 <1 RK_PA2 5 &pcfg_pull_none>;
558 pwm1m0_pins: pwm1m0-pins {
561 <4 RK_PC4 1 &pcfg_pull_none>;
564 pwm1m1_pins: pwm1m1-pins {
567 <1 RK_PA3 4 &pcfg_pull_none>;
572 pwm2m0_pins: pwm2m0-pins {
575 <4 RK_PC5 1 &pcfg_pull_none>;
578 pwm2m1_pins: pwm2m1-pins {
581 <1 RK_PA7 2 &pcfg_pull_none>;
586 pwm3m0_pins: pwm3m0-pins {
589 <4 RK_PC6 1 &pcfg_pull_none>;
592 pwm3m1_pins: pwm3m1-pins {
595 <2 RK_PA4 3 &pcfg_pull_none>;
600 pwm4m0_pins: pwm4m0-pins {
603 <4 RK_PB7 1 &pcfg_pull_none>;
606 pwm4m1_pins: pwm4m1-pins {
609 <1 RK_PA4 2 &pcfg_pull_none>;
614 pwm5m0_pins: pwm5m0-pins {
617 <4 RK_PC0 1 &pcfg_pull_none>;
620 pwm5m1_pins: pwm5m1-pins {
623 <3 RK_PC3 1 &pcfg_pull_none>;
628 pwm6m0_pins: pwm6m0-pins {
631 <4 RK_PC1 1 &pcfg_pull_none>;
634 pwm6m1_pins: pwm6m1-pins {
637 <1 RK_PC3 3 &pcfg_pull_none>;
640 pwm6m2_pins: pwm6m2-pins {
643 <3 RK_PC1 1 &pcfg_pull_none>;
648 pwm7m0_pins: pwm7m0-pins {
651 <4 RK_PC2 1 &pcfg_pull_none>;
654 pwm7m1_pins: pwm7m1-pins {
657 <1 RK_PC2 2 &pcfg_pull_none>;
662 pwr_pins: pwr-pins {
667 <4 RK_PB6 1 &pcfg_pull_none>;
672 refm0_pins: refm0-pins {
675 <0 RK_PA1 1 &pcfg_pull_none>;
678 refm1_pins: refm1-pins {
681 <3 RK_PC3 6 &pcfg_pull_none>;
686 rgmii_miim: rgmii-miim {
689 <3 RK_PB6 2 &pcfg_pull_none>,
691 <3 RK_PB7 2 &pcfg_pull_none>;
694 rgmii_rx_bus2: rgmii-rx_bus2 {
697 <3 RK_PA3 2 &pcfg_pull_none>,
699 <3 RK_PA2 2 &pcfg_pull_none>,
701 <3 RK_PC2 2 &pcfg_pull_none>;
704 rgmii_tx_bus2: rgmii-tx_bus2 {
707 <3 RK_PA1 2 &pcfg_pull_none>,
709 <3 RK_PA0 2 &pcfg_pull_none>,
711 <3 RK_PC0 2 &pcfg_pull_none>;
714 rgmii_rgmii_clk: rgmii-rgmii_clk {
717 <3 RK_PA5 2 &pcfg_pull_none>,
719 <3 RK_PA4 2 &pcfg_pull_none>;
722 rgmii_rgmii_bus: rgmii-rgmii_bus {
725 <3 RK_PA7 2 &pcfg_pull_none>,
727 <3 RK_PA6 2 &pcfg_pull_none>,
729 <3 RK_PB1 2 &pcfg_pull_none>,
731 <3 RK_PB0 2 &pcfg_pull_none>;
734 rgmii_clk: rgmii-clk {
737 <3 RK_PB4 2 &pcfg_pull_none>;
739 rgmii_txer: rgmii-txer {
742 <3 RK_PC1 2 &pcfg_pull_none>;
747 scrm0_pins: scrm0-pins {
750 <1 RK_PA2 3 &pcfg_pull_none>,
752 <1 RK_PA1 3 &pcfg_pull_none>,
754 <1 RK_PA0 3 &pcfg_pull_none>,
756 <1 RK_PA3 3 &pcfg_pull_none>;
759 scrm1_pins: scrm1-pins {
762 <2 RK_PA5 3 &pcfg_pull_none>,
766 <2 RK_PA6 3 &pcfg_pull_none>,
773 sdio0_bus4: sdio0-bus4 {
776 <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
778 <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
780 <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
782 <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>;
785 sdio0_clk: sdio0-clk {
788 <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
791 sdio0_cmd: sdio0-cmd {
794 <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
797 sdio0_det: sdio0-det {
800 <1 RK_PA6 1 &pcfg_pull_up>;
803 sdio0_pwren: sdio0-pwren {
806 <1 RK_PA7 1 &pcfg_pull_none>;
811 sdio1_bus4: sdio1-bus4 {
814 <3 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
816 <3 RK_PA7 1 &pcfg_pull_up_drv_level_2>,
818 <3 RK_PB0 1 &pcfg_pull_up_drv_level_2>,
820 <3 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
823 sdio1_clk: sdio1-clk {
826 <3 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
829 sdio1_cmd: sdio1-cmd {
832 <3 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
835 sdio1_det: sdio1-det {
838 <3 RK_PB3 1 &pcfg_pull_up>;
841 sdio1_pwren: sdio1-pwren {
844 <3 RK_PB2 1 &pcfg_pull_none>;
848 sdmmc_pins: sdmmc-pins {
849 sdmmc_bus4: sdmmc-bus4 {
852 <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
854 <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
856 <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
858 <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>;
861 sdmmc_clk: sdmmc-clk {
864 <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
867 sdmmc_cmd: sdmmc-cmd {
870 <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
873 sdmmc_det: sdmmc-det {
876 <2 RK_PA6 1 &pcfg_pull_up>;
879 sdmmc_pwren: sdmmc-pwren {
882 <4 RK_PA1 1 &pcfg_pull_none>;
887 spdifm0_pins: spdifm0-pins {
890 <4 RK_PA0 1 &pcfg_pull_none>;
893 spdifm1_pins: spdifm1-pins {
896 <1 RK_PC3 2 &pcfg_pull_none>;
899 spdifm2_pins: spdifm2-pins {
902 <3 RK_PC3 2 &pcfg_pull_none>;
907 spi0_pins: spi0-pins {
917 spi0_csn0: spi0-csn0 {
922 spi0_csn1: spi0-csn1 {
930 spi1_pins: spi1-pins {
933 <1 RK_PB6 2 &pcfg_pull_none>,
935 <1 RK_PC0 2 &pcfg_pull_none>,
937 <1 RK_PB7 2 &pcfg_pull_none>;
940 spi1_csn0: spi1-csn0 {
943 <1 RK_PC1 1 &pcfg_pull_none>;
945 spi1_csn1: spi1-csn1 {
948 <1 RK_PC2 1 &pcfg_pull_none>;
953 tsi0_pins: tsi0-pins {
956 <3 RK_PB2 3 &pcfg_pull_none>,
958 <3 RK_PB1 3 &pcfg_pull_none>,
960 <3 RK_PB5 3 &pcfg_pull_none>,
962 <3 RK_PB6 3 &pcfg_pull_none>,
964 <3 RK_PB7 3 &pcfg_pull_none>,
966 <3 RK_PA3 3 &pcfg_pull_none>,
968 <3 RK_PA2 3 &pcfg_pull_none>,
970 <3 RK_PA1 3 &pcfg_pull_none>,
972 <3 RK_PA0 3 &pcfg_pull_none>,
974 <3 RK_PC0 3 &pcfg_pull_none>,
976 <3 RK_PB4 3 &pcfg_pull_none>,
978 <3 RK_PB3 3 &pcfg_pull_none>;
983 tsi1_pins: tsi1-pins {
986 <3 RK_PA5 3 &pcfg_pull_none>,
988 <3 RK_PA4 3 &pcfg_pull_none>,
990 <3 RK_PA7 3 &pcfg_pull_none>,
992 <3 RK_PA6 3 &pcfg_pull_none>;
997 uart0m0_xfer: uart0m0-xfer {
1000 <4 RK_PC7 1 &pcfg_pull_up>,
1002 <4 RK_PD0 1 &pcfg_pull_up>;
1005 uart0m1_xfer: uart0m1-xfer {
1015 uart1m0_xfer: uart1m0-xfer {
1023 uart1m1_xfer: uart1m1-xfer {
1031 uart1_ctsn: uart1-ctsn {
1036 uart1_rtsn: uart1-rtsn {
1044 uart2m0_xfer: uart2m0-xfer {
1047 <3 RK_PA0 1 &pcfg_pull_up>,
1049 <3 RK_PA1 1 &pcfg_pull_up>;
1052 uart2m0_ctsn: uart2m0-ctsn {
1055 <3 RK_PA3 1 &pcfg_pull_none>;
1057 uart2m0_rtsn: uart2m0-rtsn {
1060 <3 RK_PA2 1 &pcfg_pull_none>;
1063 uart2m1_xfer: uart2m1-xfer {
1066 <1 RK_PB0 1 &pcfg_pull_up>,
1068 <1 RK_PB1 1 &pcfg_pull_up>;
1071 uart2m1_ctsn: uart2m1-ctsn {
1074 <1 RK_PB3 1 &pcfg_pull_none>;
1076 uart2m1_rtsn: uart2m1-rtsn {
1079 <1 RK_PB2 1 &pcfg_pull_none>;
1084 uart3m0_xfer: uart3m0-xfer {
1092 uart3m1_xfer: uart3m1-xfer {
1095 <4 RK_PB7 3 &pcfg_pull_up>,
1097 <4 RK_PC0 3 &pcfg_pull_up>;
1100 uart3_ctsn: uart3-ctsn {
1103 <4 RK_PA3 3 &pcfg_pull_none>;
1105 uart3_rtsn: uart3-rtsn {
1108 <4 RK_PA2 3 &pcfg_pull_none>;
1113 uart4_xfer: uart4-xfer {
1116 <2 RK_PA2 3 &pcfg_pull_up>,
1118 <2 RK_PA3 3 &pcfg_pull_up>;
1121 uart4_ctsn: uart4-ctsn {
1124 <2 RK_PA1 3 &pcfg_pull_none>;
1126 uart4_rtsn: uart4-rtsn {
1129 <2 RK_PA0 3 &pcfg_pull_none>;
1134 uart5m0_xfer: uart5m0-xfer {
1137 <1 RK_PA2 2 &pcfg_pull_up>,
1139 <1 RK_PA3 2 &pcfg_pull_up>;
1142 uart5m0_ctsn: uart5m0-ctsn {
1145 <1 RK_PA6 2 &pcfg_pull_none>;
1147 uart5m0_rtsn: uart5m0-rtsn {
1150 <1 RK_PA5 2 &pcfg_pull_none>;
1153 uart5m1_xfer: uart5m1-xfer {
1156 <1 RK_PD4 2 &pcfg_pull_up>,
1158 <1 RK_PD7 2 &pcfg_pull_up>;
1161 uart5m1_ctsn: uart5m1-ctsn {
1164 <1 RK_PD3 2 &pcfg_pull_none>;
1166 uart5m1_rtsn: uart5m1-rtsn {
1169 <1 RK_PD2 2 &pcfg_pull_none>;
1174 uart6m0_xfer: uart6m0-xfer {
1177 <3 RK_PA7 4 &pcfg_pull_up>,
1179 <3 RK_PA6 4 &pcfg_pull_up>;
1182 uart6m1_xfer: uart6m1-xfer {
1185 <3 RK_PC3 4 &pcfg_pull_up>,
1187 <3 RK_PC1 4 &pcfg_pull_up>;
1190 uart6_ctsn: uart6-ctsn {
1193 <3 RK_PA4 4 &pcfg_pull_none>;
1195 uart6_rtsn: uart6-rtsn {
1198 <3 RK_PA5 4 &pcfg_pull_none>;
1203 uart7m0_xfer: uart7m0-xfer {
1206 <3 RK_PB3 4 &pcfg_pull_up>,
1208 <3 RK_PB2 4 &pcfg_pull_up>;
1211 uart7m0_ctsn: uart7m0-ctsn {
1214 <3 RK_PB0 4 &pcfg_pull_none>;
1216 uart7m0_rtsn: uart7m0-rtsn {
1219 <3 RK_PB1 4 &pcfg_pull_none>;
1222 uart7m1_xfer: uart7m1-xfer {
1225 <1 RK_PB3 4 &pcfg_pull_up>,
1227 <1 RK_PB2 4 &pcfg_pull_up>;
1230 uart7m1_ctsn: uart7m1-ctsn {
1233 <1 RK_PB0 4 &pcfg_pull_none>;
1235 uart7m1_rtsn: uart7m1-rtsn {
1238 <1 RK_PB1 4 &pcfg_pull_none>;