Lines Matching +full:saradc +full:- +full:apb
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/clock/rk3368-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/thermal/thermal.h>
49 #include <dt-bindings/memory/rk3368-dmc.h>
53 interrupt-parent = <&gic>;
54 #address-cells = <2>;
55 #size-cells = <2>;
76 #address-cells = <0x2>;
77 #size-cells = <0x0>;
79 cpu-map {
111 idle-states {
112 entry-method = "psci";
114 cpu_sleep: cpu-sleep-0 {
115 compatible = "arm,idle-state";
116 arm,psci-suspend-param = <0x1010000>;
117 entry-latency-us = <0x3fffffff>;
118 exit-latency-us = <0x40000000>;
119 min-residency-us = <0xffffffff>;
125 compatible = "arm,cortex-a53", "arm,armv8";
127 cpu-idle-states = <&cpu_sleep>;
128 enable-method = "psci";
130 #cooling-cells = <2>; /* min followed by max */
135 compatible = "arm,cortex-a53", "arm,armv8";
137 cpu-idle-states = <&cpu_sleep>;
138 enable-method = "psci";
143 compatible = "arm,cortex-a53", "arm,armv8";
145 cpu-idle-states = <&cpu_sleep>;
146 enable-method = "psci";
151 compatible = "arm,cortex-a53", "arm,armv8";
153 cpu-idle-states = <&cpu_sleep>;
154 enable-method = "psci";
159 compatible = "arm,cortex-a53", "arm,armv8";
161 cpu-idle-states = <&cpu_sleep>;
162 enable-method = "psci";
164 #cooling-cells = <2>; /* min followed by max */
169 compatible = "arm,cortex-a53", "arm,armv8";
171 cpu-idle-states = <&cpu_sleep>;
172 enable-method = "psci";
177 compatible = "arm,cortex-a53", "arm,armv8";
179 cpu-idle-states = <&cpu_sleep>;
180 enable-method = "psci";
185 compatible = "arm,cortex-a53", "arm,armv8";
187 cpu-idle-states = <&cpu_sleep>;
188 enable-method = "psci";
192 arm-pmu {
193 compatible = "arm,armv8-pmuv3";
202 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
208 compatible = "arm,psci-0.2";
213 compatible = "arm,armv8-timer";
225 compatible = "fixed-clock";
226 clock-frequency = <24000000>;
227 clock-output-names = "xin24m";
228 #clock-cells = <0>;
232 compatible = "rockchip,rk3368-dmc", "syscon";
241 compatible = "rockchip,rk3368-msch", "syscon";
247 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
249 clock-freq-min-max = <400000 150000000>;
252 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
253 fifo-depth = <0x100>;
254 cd-gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_HIGH>;
260 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
262 clock-freq-min-max = <400000 150000000>;
265 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
266 fifo-depth = <0x100>;
272 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
274 clock-freq-min-max = <400000 150000000>;
277 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
278 fifo-depth = <0x100>;
283 saradc: saradc@ff100000 { label
284 compatible = "rockchip,saradc";
287 #io-channel-cells = <1>;
289 clock-names = "saradc", "apb_pclk";
294 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
297 clock-names = "spiclk", "apb_pclk";
299 pinctrl-names = "default";
300 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
301 #address-cells = <1>;
302 #size-cells = <0>;
307 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
310 clock-names = "spiclk", "apb_pclk";
312 pinctrl-names = "default";
313 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
314 #address-cells = <1>;
315 #size-cells = <0>;
320 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
323 clock-names = "spiclk", "apb_pclk";
325 pinctrl-names = "default";
326 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
327 #address-cells = <1>;
328 #size-cells = <0>;
333 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
336 #address-cells = <1>;
337 #size-cells = <0>;
338 clock-names = "i2c";
340 pinctrl-names = "default";
341 pinctrl-0 = <&i2c1_xfer>;
346 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
349 #address-cells = <1>;
350 #size-cells = <0>;
351 clock-names = "i2c";
353 pinctrl-names = "default";
354 pinctrl-0 = <&i2c3_xfer>;
359 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
362 #address-cells = <1>;
363 #size-cells = <0>;
364 clock-names = "i2c";
366 pinctrl-names = "default";
367 pinctrl-0 = <&i2c4_xfer>;
372 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
375 #address-cells = <1>;
376 #size-cells = <0>;
377 clock-names = "i2c";
379 pinctrl-names = "default";
380 pinctrl-0 = <&i2c5_xfer>;
385 compatible = "rockchip,rk-nandc";
390 clock-names = "clk_nandc", "hclk_nandc";
395 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
397 clock-frequency = <24000000>;
399 clock-names = "baudclk", "apb_pclk";
401 reg-shift = <2>;
402 reg-io-width = <4>;
403 pinctrl-names = "default";
404 pinctrl-0 = <&uart0_xfer>;
409 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
411 clock-frequency = <24000000>;
413 clock-names = "baudclk", "apb_pclk";
415 reg-shift = <2>;
416 reg-io-width = <4>;
417 pinctrl-names = "default";
418 pinctrl-1 = <&uart0_xfer>;
423 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
425 clock-frequency = <24000000>;
427 clock-names = "baudclk", "apb_pclk";
429 reg-shift = <2>;
430 reg-io-width = <4>;
431 pinctrl-names = "default";
432 pinctrl-0 = <&uart3_xfer>;
437 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
439 clock-frequency = <24000000>;
441 clock-names = "baudclk", "apb_pclk";
443 reg-shift = <2>;
444 reg-io-width = <4>;
445 pinctrl-names = "default";
446 pinctrl-0 = <&uart4_xfer>;
450 thermal-zones {
452 polling-delay-passive = <100>; /* milliseconds */
453 polling-delay = <5000>; /* milliseconds */
455 thermal-sensors = <&tsadc 0>;
475 cooling-maps {
478 cooling-device =
483 cooling-device =
490 polling-delay-passive = <100>; /* milliseconds */
491 polling-delay = <5000>; /* milliseconds */
493 thermal-sensors = <&tsadc 1>;
508 cooling-maps {
511 cooling-device =
519 compatible = "rockchip,rk3368-tsadc";
523 clock-names = "tsadc", "apb_pclk";
525 reset-names = "tsadc-apb";
526 pinctrl-names = "init", "default", "sleep";
527 pinctrl-0 = <&otp_gpio>;
528 pinctrl-1 = <&otp_out>;
529 pinctrl-2 = <&otp_gpio>;
530 #thermal-sensor-cells = <1>;
531 rockchip,hw-tshut-temp = <95000>;
536 compatible = "rockchip,rk3368-gmac";
539 interrupt-names = "macirq";
545 clock-names = "stmmaceth",
553 compatible = "generic-ehci";
557 clock-names = "usbhost";
559 phy-names = "usb";
564 compatible = "generic-ohci";
568 clock-names = "usbhost", "utmi";
570 phy-names = "usb";
575 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
580 clock-names = "otg";
582 g-np-tx-fifo-size = <16>;
583 g-rx-fifo-size = <275>;
584 g-tx-fifo-size = <256 128 128 64 64 32>;
585 g-use-dma;
587 phy-names = "usb2-phy";
592 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
595 clock-names = "i2c";
597 pinctrl-names = "default";
598 pinctrl-0 = <&i2c0_xfer>;
599 #address-cells = <1>;
600 #size-cells = <0>;
605 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
608 #address-cells = <1>;
609 #size-cells = <0>;
610 clock-names = "i2c";
612 pinctrl-names = "default";
613 pinctrl-0 = <&i2c2_xfer>;
618 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
620 #pwm-cells = <3>;
621 pinctrl-names = "active";
622 pinctrl-0 = <&pwm0_pin>;
624 clock-names = "pwm";
629 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
631 #pwm-cells = <3>;
632 pinctrl-names = "active";
633 pinctrl-0 = <&pwm1_pin>;
635 clock-names = "pwm";
640 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
642 #pwm-cells = <3>;
644 clock-names = "pwm";
649 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
651 #pwm-cells = <3>;
652 pinctrl-names = "active";
653 pinctrl-0 = <&pwm3_pin>;
655 clock-names = "pwm";
660 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
662 clock-frequency = <24000000>;
664 clock-names = "baudclk", "apb_pclk";
666 pinctrl-names = "default";
667 pinctrl-0 = <&uart2_xfer>;
668 reg-shift = <2>;
669 reg-io-width = <4>;
674 compatible = "rockchip,rk3368-mailbox";
681 clock-names = "pclk_mailbox";
682 #mbox-cells = <1>;
686 compatible = "rockchip,rk3368-pmugrf", "syscon";
691 compatible = "rockchip,rk3368-sgrf", "syscon";
695 cru: clock-controller@ff760000 {
696 compatible = "rockchip,rk3368-cru";
699 #clock-cells = <1>;
700 #reset-cells = <1>;
704 compatible = "rockchip,rk3368-grf", "syscon";
706 #address-cells = <1>;
707 #size-cells = <1>;
709 u2phy: usb2-phy@700 {
710 compatible = "rockchip,rk3368-usb2phy";
713 clock-names = "phyclk";
714 #clock-cells = <0>;
715 clock-output-names = "usbotg_out";
716 assigned-clocks = <&cru SCLK_USBPHY480M>;
717 assigned-clock-parents = <&u2phy>;
720 u2phy_otg: otg-port {
721 #phy-cells = <0>;
725 interrupt-names = "otg-bvalid", "otg-id",
730 u2phy_host: host-port {
731 #phy-cells = <0>;
733 interrupt-names = "linestate";
740 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
748 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
754 compatible = "rockchip,rk3368-crypto";
756 clock-names = "sclk_crypto";
761 gic: interrupt-controller@ffb71000 {
762 compatible = "arm,gic-400";
763 interrupt-controller;
764 #interrupt-cells = <3>;
765 #address-cells = <0>;
776 compatible = "rockchip,rk3368-pinctrl";
779 #address-cells = <0x2>;
780 #size-cells = <0x2>;
784 compatible = "rockchip,gpio-bank";
789 gpio-controller;
790 #gpio-cells = <0x2>;
792 interrupt-controller;
793 #interrupt-cells = <0x2>;
797 compatible = "rockchip,gpio-bank";
802 gpio-controller;
803 #gpio-cells = <0x2>;
805 interrupt-controller;
806 #interrupt-cells = <0x2>;
810 compatible = "rockchip,gpio-bank";
815 gpio-controller;
816 #gpio-cells = <0x2>;
818 interrupt-controller;
819 #interrupt-cells = <0x2>;
823 compatible = "rockchip,gpio-bank";
828 gpio-controller;
829 #gpio-cells = <0x2>;
831 interrupt-controller;
832 #interrupt-cells = <0x2>;
835 pcfg_pull_up: pcfg-pull-up {
836 bias-pull-up;
839 pcfg_pull_down: pcfg-pull-down {
840 bias-pull-down;
843 pcfg_pull_none: pcfg-pull-none {
844 bias-disable;
847 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
848 bias-disable;
849 drive-strength = <12>;
853 emmc_clk: emmc-clk {
857 emmc_cmd: emmc-cmd {
861 emmc_pwr: emmc-pwr {
865 emmc_bus1: emmc-bus1 {
869 emmc_bus4: emmc-bus4 {
876 emmc_bus8: emmc-bus8 {
889 rgmii_pins: rgmii-pins {
907 rmii_pins: rmii-pins {
922 i2c0_xfer: i2c0-xfer {
929 i2c1_xfer: i2c1-xfer {
936 i2c2_xfer: i2c2-xfer {
943 i2c3_xfer: i2c3-xfer {
950 i2c4_xfer: i2c4-xfer {
957 i2c5_xfer: i2c5-xfer {
964 pwm0_pin: pwm0-pin {
970 pwm1_pin: pwm1-pin {
976 pwm3_pin: pwm3-pin {
982 sdio0_bus1: sdio0-bus1 {
986 sdio0_bus4: sdio0-bus4 {
993 sdio0_cmd: sdio0-cmd {
997 sdio0_clk: sdio0-clk {
1001 sdio0_cd: sdio0-cd {
1005 sdio0_wp: sdio0-wp {
1009 sdio0_pwr: sdio0-pwr {
1013 sdio0_bkpwr: sdio0-bkpwr {
1017 sdio0_int: sdio0-int {
1023 sdmmc_clk: sdmmc-clk {
1027 sdmmc_cmd: sdmmc-cmd {
1031 sdmmc_cd: sdmmc-cd {
1035 sdmmc_bus1: sdmmc-bus1 {
1039 sdmmc_bus4: sdmmc-bus4 {
1048 spi0_clk: spi0-clk {
1051 spi0_cs0: spi0-cs0 {
1054 spi0_cs1: spi0-cs1 {
1057 spi0_tx: spi0-tx {
1060 spi0_rx: spi0-rx {
1066 spi1_clk: spi1-clk {
1069 spi1_cs0: spi1-cs0 {
1072 spi1_cs1: spi1-cs1 {
1075 spi1_rx: spi1-rx {
1078 spi1_tx: spi1-tx {
1084 spi2_clk: spi2-clk {
1087 spi2_cs0: spi2-cs0 {
1090 spi2_rx: spi2-rx {
1093 spi2_tx: spi2-tx {
1099 otp_gpio: otp-gpio {
1103 otp_out: otp-out {
1109 uart0_xfer: uart0-xfer {
1114 uart0_cts: uart0-cts {
1118 uart0_rts: uart0-rts {
1124 uart1_xfer: uart1-xfer {
1129 uart1_cts: uart1-cts {
1133 uart1_rts: uart1-rts {
1139 uart2_xfer: uart2-xfer {
1147 uart3_xfer: uart3-xfer {
1152 uart3_cts: uart3-cts {
1156 uart3_rts: uart3-rts {
1162 uart4_xfer: uart4-xfer {
1167 uart4_cts: uart4-cts {
1171 uart4_rts: uart4-rts {