Lines Matching +full:saradc +full:- +full:apb
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/clock/rk3328-cru.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
34 #address-cells = <2>;
35 #size-cells = <0>;
39 compatible = "arm,cortex-a53", "arm,armv8";
41 enable-method = "psci";
43 operating-points-v2 = <&cpu0_opp_table>;
47 compatible = "arm,cortex-a53", "arm,armv8";
49 enable-method = "psci";
53 compatible = "arm,cortex-a53", "arm,armv8";
55 enable-method = "psci";
59 compatible = "arm,cortex-a53", "arm,armv8";
61 enable-method = "psci";
66 compatible = "operating-points-v2";
67 opp-shared;
70 opp-hz = /bits/ 64 <408000000>;
71 opp-microvolt = <950000>;
72 clock-latency-ns = <40000>;
73 opp-suspend;
76 opp-hz = /bits/ 64 <600000000>;
77 opp-microvolt = <950000>;
78 clock-latency-ns = <40000>;
81 opp-hz = /bits/ 64 <816000000>;
82 opp-microvolt = <1000000>;
83 clock-latency-ns = <40000>;
86 opp-hz = /bits/ 64 <1008000000>;
87 opp-microvolt = <1100000>;
88 clock-latency-ns = <40000>;
91 opp-hz = /bits/ 64 <1200000000>;
92 opp-microvolt = <1225000>;
93 clock-latency-ns = <40000>;
96 opp-hz = /bits/ 64 <1296000000>;
97 opp-microvolt = <1300000>;
98 clock-latency-ns = <40000>;
102 arm-pmu {
103 compatible = "arm,cortex-a53-pmu";
108 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
112 compatible = "arm,psci-1.0";
117 compatible = "arm,armv8-timer";
125 compatible = "fixed-clock";
126 #clock-cells = <0>;
127 clock-frequency = <24000000>;
128 clock-output-names = "xin24m";
132 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
136 clock-names = "i2s_clk", "i2s_hclk";
138 #dma-cells = <2>;
139 dma-names = "tx", "rx";
144 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
148 clock-names = "i2s_clk", "i2s_hclk";
150 #dma-cells = <2>;
151 dma-names = "tx", "rx";
156 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
160 clock-names = "i2s_clk", "i2s_hclk";
162 #dma-cells = <2>;
163 dma-names = "tx", "rx";
164 pinctrl-names = "default", "sleep";
165 pinctrl-0 = <&i2s2m0_mclk
171 pinctrl-1 = <&i2s2m0_sleep>;
176 compatible = "rockchip,rk3328-spdif";
180 clock-names = "mclk", "hclk";
182 #dma-cells = <1>;
183 dma-names = "tx";
184 pinctrl-names = "default";
185 pinctrl-0 = <&spdifm2_tx>;
190 compatible = "rockchip,rk322x-crypto";
192 clock-names = "sclk_crypto";
198 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
200 #address-cells = <1>;
201 #size-cells = <1>;
203 io_domains: io-domains {
204 compatible = "rockchip,rk3328-io-voltage-domain";
210 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
214 clock-names = "baudclk", "apb_pclk";
215 reg-shift = <2>;
216 reg-io-width = <4>;
218 #dma-cells = <2>;
219 pinctrl-names = "default";
220 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
225 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
229 clock-names = "sclk_uart", "pclk_uart";
230 reg-shift = <2>;
231 reg-io-width = <4>;
233 #dma-cells = <2>;
234 pinctrl-names = "default";
235 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
240 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
244 clock-names = "baudclk", "apb_pclk";
245 clock-frequency = <24000000>;
246 reg-shift = <2>;
247 reg-io-width = <4>;
249 #dma-cells = <2>;
250 pinctrl-names = "default";
251 pinctrl-0 = <&uart2m1_xfer>;
255 pmu: power-management@ff140000 {
256 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
261 compatible = "rockchip,rk3328-i2c";
264 #address-cells = <1>;
265 #size-cells = <0>;
267 clock-names = "i2c", "pclk";
268 pinctrl-names = "default";
269 pinctrl-0 = <&i2c0_xfer>;
274 compatible = "rockchip,rk3328-i2c";
277 #address-cells = <1>;
278 #size-cells = <0>;
280 clock-names = "i2c", "pclk";
281 pinctrl-names = "default";
282 pinctrl-0 = <&i2c1_xfer>;
287 compatible = "rockchip,rk3328-i2c";
290 #address-cells = <1>;
291 #size-cells = <0>;
293 clock-names = "i2c", "pclk";
294 pinctrl-names = "default";
295 pinctrl-0 = <&i2c2_xfer>;
300 compatible = "rockchip,rk3328-i2c";
303 #address-cells = <1>;
304 #size-cells = <0>;
306 clock-names = "i2c", "pclk";
307 pinctrl-names = "default";
308 pinctrl-0 = <&i2c3_xfer>;
313 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
316 #address-cells = <1>;
317 #size-cells = <0>;
319 clock-names = "spiclk", "apb_pclk";
321 #dma-cells = <2>;
322 dma-names = "tx", "rx";
323 pinctrl-names = "default";
324 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
329 compatible = "snps,dw-wdt";
336 compatible = "simple-bus";
337 #address-cells = <2>;
338 #size-cells = <2>;
347 clock-names = "apb_pclk";
348 #dma-cells = <1>;
352 saradc: saradc@ff280000 { label
353 compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
356 #io-channel-cells = <1>;
358 clock-names = "saradc", "apb_pclk";
360 reset-names = "saradc-apb";
365 compatible = "rockchip,rk3328-dmc";
374 cru: clock-controller@ff440000 {
375 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
378 #clock-cells = <1>;
379 #reset-cells = <1>;
380 assigned-clocks =
405 assigned-clock-parents =
409 assigned-clock-rates =
437 compatible = "rockchip,rk3328-usb2phy-grf",
438 "simple-mfd", "syscon";
440 #address-cells = <1>;
441 #size-cells = <1>;
443 u2phy: usb2-phy@100 {
444 compatible = "rockchip,rk3328-usb2phy";
446 #phy-cells = <1>;
449 u2phy_host: host-port {
450 #phy-cells = <0>;
452 interrupt-names = "linestate";
456 u2phy_otg: otg-port {
457 #phy-cells = <0>;
461 interrupt-names = "otg-bvalid", "otg-id",
469 compatible = "rockchip,usb3phy-grf", "syscon";
473 u3phy: usb3-phy@ff470000 {
474 compatible = "rockchip,rk3328-u3phy";
479 interrupt-names = "linestate";
481 clock-names = "u3phy-otg", "u3phy-pipe";
488 reset-names = "u3phy-u2-por", "u3phy-u3-por",
489 "u3phy-pipe-mac", "u3phy-utmi-mac",
490 "u3phy-utmi-apb", "u3phy-pipe-apb";
491 #address-cells = <2>;
492 #size-cells = <2>;
498 #phy-cells = <0>;
504 #phy-cells = <0>;
510 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
512 max-frequency = <150000000>;
515 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
516 fifo-depth = <0x100>;
522 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
524 max-frequency = <150000000>;
527 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
528 fifo-depth = <0x100>;
534 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
536 max-frequency = <150000000>;
539 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
540 fifo-depth = <0x100>;
546 compatible = "rockchip,rk3328-gmac";
550 interrupt-names = "macirq";
555 clock-names = "stmmaceth", "mac_clk_rx",
560 reset-names = "stmmaceth";
565 compatible = "rockchip,rk3328-gmac";
569 interrupt-names = "macirq";
574 clock-names = "stmmaceth", "mac_clk_rx",
579 reset-names = "stmmaceth", "mac-phy";
580 phy-mode = "rmii";
581 phy-handle = <&phy>;
582 pinctrl-names = "default";
583 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
587 compatible = "snps,dwmac-mdio";
588 #address-cells = <1>;
589 #size-cells = <0>;
592 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
594 phy-is-integrated;
600 compatible = "generic-ehci";
604 phy-names = "usb";
609 compatible = "generic-ohci";
613 phy-names = "usb";
618 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
622 hnp-srp-disable;
625 phy-names = "usb";
630 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
632 max-frequency = <150000000>;
634 clock-names = "biu", "ciu";
635 fifo-depth = <0x100>;
641 compatible = "rockchip,rk3328-dwc3";
644 clock-names = "ref_clk", "suspend_clk",
646 #address-cells = <2>;
647 #size-cells = <2>;
657 phy-names = "usb2-phy", "usb3-phy";
660 snps,dis-u2-freeclk-exists-quirk;
662 snps,dis-u3-autosuspend-quirk;
664 snps,dis-del-phy-power-chg-quirk;
665 snps,tx-ipgap-linecheck-dis-quirk;
666 snps,xhci-trb-ent-quirk;
671 gic: interrupt-controller@ffb70000 {
672 compatible = "arm,gic-400";
673 #interrupt-cells = <3>;
674 #address-cells = <0>;
675 interrupt-controller;
685 compatible = "rockchip,rk3328-pinctrl";
687 #address-cells = <2>;
688 #size-cells = <2>;
692 compatible = "rockchip,gpio-bank";
697 gpio-controller;
698 #gpio-cells = <2>;
700 interrupt-controller;
701 #interrupt-cells = <2>;
705 compatible = "rockchip,gpio-bank";
710 gpio-controller;
711 #gpio-cells = <2>;
713 interrupt-controller;
714 #interrupt-cells = <2>;
718 compatible = "rockchip,gpio-bank";
723 gpio-controller;
724 #gpio-cells = <2>;
726 interrupt-controller;
727 #interrupt-cells = <2>;
731 compatible = "rockchip,gpio-bank";
736 gpio-controller;
737 #gpio-cells = <2>;
739 interrupt-controller;
740 #interrupt-cells = <2>;
743 pcfg_pull_up: pcfg-pull-up {
744 bias-pull-up;
747 pcfg_pull_down: pcfg-pull-down {
748 bias-pull-down;
751 pcfg_pull_none: pcfg-pull-none {
752 bias-disable;
755 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
756 bias-disable;
757 drive-strength = <2>;
760 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
761 bias-pull-up;
762 drive-strength = <2>;
765 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
766 bias-pull-up;
767 drive-strength = <4>;
770 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
771 bias-disable;
772 drive-strength = <4>;
775 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
776 bias-pull-down;
777 drive-strength = <4>;
780 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
781 bias-disable;
782 drive-strength = <8>;
785 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
786 bias-pull-up;
787 drive-strength = <8>;
790 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
791 bias-disable;
792 drive-strength = <12>;
795 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
796 bias-pull-up;
797 drive-strength = <12>;
800 pcfg_output_high: pcfg-output-high {
801 output-high;
804 pcfg_output_low: pcfg-output-low {
805 output-low;
808 pcfg_input_high: pcfg-input-high {
809 bias-pull-up;
810 input-enable;
813 pcfg_input: pcfg-input {
814 input-enable;
818 i2c0_xfer: i2c0-xfer {
826 i2c1_xfer: i2c1-xfer {
834 i2c2_xfer: i2c2-xfer {
842 i2c3_xfer: i2c3-xfer {
847 i2c3_gpio: i2c3-gpio {
855 hdmii2c_xfer: hdmii2c-xfer {
863 uart0_xfer: uart0-xfer {
869 uart0_cts: uart0-cts {
874 uart0_rts: uart0-rts {
879 uart0_rts_gpio: uart0-rts-gpio {
886 uart1_xfer: uart1-xfer {
892 uart1_cts: uart1-cts {
897 uart1_rts: uart1-rts {
902 uart1_rts_gpio: uart1-rts-gpio {
908 uart2-0 {
909 uart2m0_xfer: uart2m0-xfer {
916 uart2-1 {
917 uart2m1_xfer: uart2m1-xfer {
924 spi0-0 {
925 spi0m0_clk: spi0m0-clk {
930 spi0m0_cs0: spi0m0-cs0 {
935 spi0m0_tx: spi0m0-tx {
940 spi0m0_rx: spi0m0-rx {
945 spi0m0_cs1: spi0m0-cs1 {
951 spi0-1 {
952 spi0m1_clk: spi0m1-clk {
957 spi0m1_cs0: spi0m1-cs0 {
962 spi0m1_tx: spi0m1-tx {
967 spi0m1_rx: spi0m1-rx {
972 spi0m1_cs1: spi0m1-cs1 {
978 spi0-2 {
979 spi0m2_clk: spi0m2-clk {
984 spi0m2_cs0: spi0m2-cs0 {
989 spi0m2_tx: spi0m2-tx {
994 spi0m2_rx: spi0m2-rx {
1001 i2s1_mclk: i2s1-mclk {
1006 i2s1_sclk: i2s1-sclk {
1011 i2s1_lrckrx: i2s1-lrckrx {
1016 i2s1_lrcktx: i2s1-lrcktx {
1021 i2s1_sdi: i2s1-sdi {
1026 i2s1_sdo: i2s1-sdo {
1031 i2s1_sdio1: i2s1-sdio1 {
1036 i2s1_sdio2: i2s1-sdio2 {
1041 i2s1_sdio3: i2s1-sdio3 {
1046 i2s1_sleep: i2s1-sleep {
1060 i2s2-0 {
1061 i2s2m0_mclk: i2s2m0-mclk {
1066 i2s2m0_sclk: i2s2m0-sclk {
1071 i2s2m0_lrckrx: i2s2m0-lrckrx {
1076 i2s2m0_lrcktx: i2s2m0-lrcktx {
1081 i2s2m0_sdi: i2s2m0-sdi {
1086 i2s2m0_sdo: i2s2m0-sdo {
1091 i2s2m0_sleep: i2s2m0-sleep {
1102 i2s2-1 {
1103 i2s2m1_mclk: i2s2m1-mclk {
1108 i2s2m1_sclk: i2s2m1-sclk {
1113 i2s2m1_lrckrx: i2sm1-lrckrx {
1118 i2s2m1_lrcktx: i2s2m1-lrcktx {
1123 i2s2m1_sdi: i2s2m1-sdi {
1128 i2s2m1_sdo: i2s2m1-sdo {
1133 i2s2m1_sleep: i2s2m1-sleep {
1143 spdif-0 {
1144 spdifm0_tx: spdifm0-tx {
1150 spdif-1 {
1151 spdifm1_tx: spdifm1-tx {
1157 spdif-2 {
1158 spdifm2_tx: spdifm2-tx {
1164 sdmmc0-0 {
1165 sdmmc0m0_pwren: sdmmc0m0-pwren {
1170 sdmmc0m0_gpio: sdmmc0m0-gpio {
1176 sdmmc0-1 {
1177 sdmmc0m1_pwren: sdmmc0m1-pwren {
1182 sdmmc0m1_gpio: sdmmc0m1-gpio {
1189 sdmmc0_clk: sdmmc0-clk {
1194 sdmmc0_cmd: sdmmc0-cmd {
1199 sdmmc0_dectn: sdmmc0-dectn {
1204 sdmmc0_wrprt: sdmmc0-wrprt {
1209 sdmmc0_bus1: sdmmc0-bus1 {
1214 sdmmc0_bus4: sdmmc0-bus4 {
1222 sdmmc0_gpio: sdmmc0-gpio {
1236 sdmmc0ext_clk: sdmmc0ext-clk {
1241 sdmmc0ext_cmd: sdmmc0ext-cmd {
1246 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1251 sdmmc0ext_dectn: sdmmc0ext-dectn {
1256 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1261 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1269 sdmmc0ext_gpio: sdmmc0ext-gpio {
1283 sdmmc1_clk: sdmmc1-clk {
1288 sdmmc1_cmd: sdmmc1-cmd {
1293 sdmmc1_pwren: sdmmc1-pwren {
1298 sdmmc1_wrprt: sdmmc1-wrprt {
1303 sdmmc1_dectn: sdmmc1-dectn {
1308 sdmmc1_bus1: sdmmc1-bus1 {
1313 sdmmc1_bus4: sdmmc1-bus4 {
1321 sdmmc1_gpio: sdmmc1-gpio {
1336 emmc_clk: emmc-clk {
1341 emmc_cmd: emmc-cmd {
1346 emmc_pwren: emmc-pwren {
1351 emmc_rstnout: emmc-rstnout {
1356 emmc_bus1: emmc-bus1 {
1361 emmc_bus4: emmc-bus4 {
1369 emmc_bus8: emmc-bus8 {
1383 pwm0_pin: pwm0-pin {
1390 pwm1_pin: pwm1-pin {
1397 pwm2_pin: pwm2-pin {
1404 pwmir_pin: pwmir-pin {
1410 gmac-0 {
1411 rgmiim0_pins: rgmiim0-pins {
1445 rmiim0_pins: rmiim0-pins {
1470 gmac-1 {
1471 rgmiim1_pins: rgmiim1-pins {
1520 rmiim1_pins: rmiim1-pins {
1559 fephyled_speed100: fephyled-speed100 {
1564 fephyled_speed10: fephyled-speed10 {
1569 fephyled_duplex: fephyled-duplex {
1574 fephyled_rxm0: fephyled-rxm0 {
1579 fephyled_txm0: fephyled-txm0 {
1584 fephyled_linkm0: fephyled-linkm0 {
1589 fephyled_rxm1: fephyled-rxm1 {
1594 fephyled_txm1: fephyled-txm1 {
1599 fephyled_linkm1: fephyled-linkm1 {
1606 tsadc_int: tsadc-int {
1610 tsadc_gpio: tsadc-gpio {
1617 hdmi_cec: hdmi-cec {
1622 hdmi_hpd: hdmi-hpd {
1628 cif-0 {
1629 dvp_d2d9_m0:dvp-d2d9-m0 {
1658 cif-1 {
1659 dvp_d2d9_m1:dvp-d2d9-m1 {