Lines Matching +full:0 +full:xff100000
35 #size-cells = <0>;
37 cpu0: cpu@0 {
40 reg = <0x0 0x0>;
48 reg = <0x0 0x1>;
54 reg = <0x0 0x2>;
60 reg = <0x0 0x3>;
126 #clock-cells = <0>;
133 reg = <0x0 0xff000000 0x0 0x1000>;
145 reg = <0x0 0xff010000 0x0 0x1000>;
157 reg = <0x0 0xff020000 0x0 0x1000>;
161 dmas = <&dmac 0>, <&dmac 1>;
165 pinctrl-0 = <&i2s2m0_mclk
177 reg = <0x0 0xff030000 0x0 0x1000>;
185 pinctrl-0 = <&spdifm2_tx>;
191 reg = <0x0 0xff060000 0x0 0x10000>;
199 reg = <0x0 0xff100000 0x0 0x1000>;
211 reg = <0x0 0xff110000 0x0 0x100>;
220 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
226 reg = <0x0 0xff120000 0x0 0x100>;
235 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
241 reg = <0x0 0xff130000 0x0 0x100>;
251 pinctrl-0 = <&uart2m1_xfer>;
257 reg = <0x0 0xff140000 0x0 0x1000>;
262 reg = <0x0 0xff150000 0x0 0x1000>;
265 #size-cells = <0>;
269 pinctrl-0 = <&i2c0_xfer>;
275 reg = <0x0 0xff160000 0x0 0x1000>;
278 #size-cells = <0>;
282 pinctrl-0 = <&i2c1_xfer>;
288 reg = <0x0 0xff170000 0x0 0x1000>;
291 #size-cells = <0>;
295 pinctrl-0 = <&i2c2_xfer>;
301 reg = <0x0 0xff180000 0x0 0x1000>;
304 #size-cells = <0>;
308 pinctrl-0 = <&i2c3_xfer>;
314 reg = <0x0 0xff190000 0x0 0x1000>;
317 #size-cells = <0>;
324 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
330 reg = <0x0 0xff1a0000 0x0 0x100>;
343 reg = <0x0 0xff1f0000 0x0 0x4000>;
344 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
354 reg = <0x0 0xff280000 0x0 0x100>;
366 reg = <0x0 0xff400000 0x0 0x1000
367 0x0 0xff780000 0x0 0x3000
368 0x0 0xff100000 0x0 0x1000
369 0x0 0xff440000 0x0 0x1000
370 0x0 0xff720000 0x0 0x1000
371 0x0 0xff798000 0x0 0x1000>;
376 reg = <0x0 0xff440000 0x0 0x1000>;
410 <0>, <61440000>,
411 <0>, <24000000>,
439 reg = <0x0 0xff450000 0x0 0x10000>;
445 reg = <0x100 0x10>;
450 #phy-cells = <0>;
457 #phy-cells = <0>;
470 reg = <0x0 0xff460000 0x0 0x1000>;
475 reg = <0x0 0xff470000 0x0 0x0>;
497 reg = <0x0 0xff470000 0x0 0x8000>;
498 #phy-cells = <0>;
503 reg = <0x0 0xff478000 0x0 0x8000>;
504 #phy-cells = <0>;
511 reg = <0x0 0xff500000 0x0 0x4000>;
516 fifo-depth = <0x100>;
523 reg = <0x0 0xff510000 0x0 0x4000>;
528 fifo-depth = <0x100>;
535 reg = <0x0 0xff520000 0x0 0x4000>;
540 fifo-depth = <0x100>;
547 reg = <0x0 0xff540000 0x0 0x10000>;
566 reg = <0x0 0xff550000 0x0 0x10000>;
583 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
589 #size-cells = <0>;
591 phy: phy@0 {
593 reg = <0>;
601 reg = <0x0 0xff5c0000 0x0 0x10000>;
610 reg = <0x0 0xff5d0000 0x0 0x10000>;
620 reg = <0x0 0xff580000 0x0 0x40000>;
631 reg = <0x0 0xff5f0000 0x0 0x4000>;
635 fifo-depth = <0x100>;
653 reg = <0x0 0xff600000 0x0 0x100000>;
674 #address-cells = <0>;
676 reg = <0x0 0xff811000 0 0x1000>,
677 <0x0 0xff812000 0 0x2000>,
678 <0x0 0xff814000 0 0x2000>,
679 <0x0 0xff816000 0 0x2000>;
693 reg = <0x0 0xff210000 0x0 0x100>;
706 reg = <0x0 0xff220000 0x0 0x100>;
719 reg = <0x0 0xff230000 0x0 0x100>;
732 reg = <0x0 0xff240000 0x0 0x100>;
844 <0 5 RK_FUNC_2 &pcfg_pull_none>,
845 <0 6 RK_FUNC_2 &pcfg_pull_none>;
849 <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
850 <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
857 <0 5 RK_FUNC_1 &pcfg_pull_none>,
858 <0 6 RK_FUNC_1 &pcfg_pull_none>;
908 uart2-0 {
911 <1 0 RK_FUNC_2 &pcfg_pull_up>,
919 <2 0 RK_FUNC_1 &pcfg_pull_up>,
924 spi0-0 {
981 <3 0 RK_FUNC_4 &pcfg_pull_up>;
1060 i2s2-0 {
1110 <3 0 RK_FUNC_6 &pcfg_pull_none>;
1136 <3 0 RK_FUNC_GPIO &pcfg_input_high>,
1143 spdif-0 {
1146 <0 27 RK_FUNC_1 &pcfg_pull_none>;
1160 <0 2 RK_FUNC_2 &pcfg_pull_none>;
1164 sdmmc0-0 {
1179 <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
1184 <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1211 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1216 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1231 <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1243 <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1271 <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1358 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1363 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1371 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1410 gmac-0 {
1414 <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1416 <0 10 RK_FUNC_1 &pcfg_pull_none>,
1418 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1420 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1422 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1424 <0 25 RK_FUNC_1 &pcfg_pull_none>,
1426 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1428 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1430 <0 15 RK_FUNC_1 &pcfg_pull_none>,
1432 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1434 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1436 <0 20 RK_FUNC_1 &pcfg_pull_none>,
1438 <0 21 RK_FUNC_1 &pcfg_pull_none>,
1440 <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
1442 <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
1448 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1450 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1452 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1454 <0 13 RK_FUNC_1 &pcfg_pull_none>,
1456 <0 25 RK_FUNC_1 &pcfg_pull_none>,
1458 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1460 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1462 <0 15 RK_FUNC_1 &pcfg_pull_none>,
1464 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1466 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
1505 <0 8 RK_FUNC_1 &pcfg_pull_none>,
1507 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1509 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1511 <0 16 RK_FUNC_1 &pcfg_pull_none>,
1513 <0 17 RK_FUNC_1 &pcfg_pull_none>,
1515 <0 23 RK_FUNC_1 &pcfg_pull_none>,
1517 <0 22 RK_FUNC_1 &pcfg_pull_none>;
1544 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1546 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1548 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1550 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1552 <0 16 RK_FUNC_1 &pcfg_pull_none>,
1554 <0 17 RK_FUNC_1 &pcfg_pull_none>;
1561 <0 31 RK_FUNC_1 &pcfg_pull_none>;
1566 <0 30 RK_FUNC_1 &pcfg_pull_none>;
1571 <0 30 RK_FUNC_2 &pcfg_pull_none>;
1576 <0 29 RK_FUNC_1 &pcfg_pull_none>;
1581 <0 29 RK_FUNC_2 &pcfg_pull_none>;
1586 <0 28 RK_FUNC_1 &pcfg_pull_none>;
1619 <0 3 RK_FUNC_1 &pcfg_pull_none>;
1624 <0 4 RK_FUNC_1 &pcfg_pull_down>;
1628 cif-0 {
1650 <3 0 RK_FUNC_2 &pcfg_pull_none>,
1680 <3 0 RK_FUNC_2 &pcfg_pull_none>,