Lines Matching +full:gpio +full:- +full:mosi
4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/clock/rk3308-cru.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
34 #address-cells = <2>;
35 #size-cells = <0>;
39 compatible = "arm,cortex-a35", "arm,armv8";
41 enable-method = "psci";
46 compatible = "arm,cortex-a35", "arm,armv8";
48 enable-method = "psci";
53 compatible = "arm,cortex-a35", "arm,armv8";
55 enable-method = "psci";
60 compatible = "arm,cortex-a35", "arm,armv8";
62 enable-method = "psci";
66 arm-pmu {
67 compatible = "arm,cortex-a53-pmu";
72 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
75 mac_clkin: external-mac-clock {
76 compatible = "fixed-clock";
77 clock-frequency = <50000000>;
78 clock-output-names = "mac_clkin";
79 #clock-cells = <0>;
82 display_subsystem: display-subsystem {
83 compatible = "rockchip,display-subsystem";
88 route_rgb: route-rgb {
100 compatible = "rockchip,rk3308-dmc";
105 compatible = "arm,psci-1.0";
110 compatible = "arm,armv8-timer";
115 clock-frequency = <24000000>;
120 compatible = "fixed-clock";
121 #clock-cells = <0>;
122 clock-frequency = <24000000>;
123 clock-output-names = "xin24m";
128 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd";
133 compatible = "rockchip,rk3308-usb2phy-grf", "syscon",
134 "simple-mfd";
136 #address-cells = <1>;
137 #size-cells = <1>;
139 u2phy: usb2-phy@100 {
140 compatible = "rockchip,rk3308-usb2phy",
141 "rockchip,rk3328-usb2phy";
144 clock-names = "phyclk";
145 #clock-cells = <0>;
146 assigned-clocks = <&cru USB480M>;
147 assigned-clock-parents = <&u2phy>;
148 clock-output-names = "usb480m_phy";
151 u2phy_host: host-port {
152 #phy-cells = <0>;
154 interrupt-names = "linestate";
158 u2phy_otg: otg-port {
159 #phy-cells = <0>;
163 interrupt-names = "otg-bvalid", "otg-id",
171 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
175 clock-names = "baudclk", "apb_pclk";
176 reg-shift = <2>;
177 reg-io-width = <4>;
182 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
186 clock-names = "baudclk", "apb_pclk";
187 reg-shift = <2>;
188 reg-io-width = <4>;
193 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
197 clock-names = "baudclk", "apb_pclk";
198 reg-shift = <2>;
199 reg-io-width = <4>;
204 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
208 clock-names = "baudclk", "apb_pclk";
209 reg-shift = <2>;
210 reg-io-width = <4>;
215 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
219 clock-names = "baudclk", "apb_pclk";
220 reg-shift = <2>;
221 reg-io-width = <4>;
226 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
229 #address-cells = <1>;
230 #size-cells = <0>;
232 clock-names = "spiclk", "apb_pclk";
233 pinctrl-names = "default", "high_speed";
234 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>;
235 pinctrl-1 = <&spi0_clk_hs &spi0_csn0 &spi0_miso_hs &spi0_mosi_hs>;
240 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
243 #address-cells = <1>;
244 #size-cells = <0>;
246 clock-names = "spiclk", "apb_pclk";
247 pinctrl-names = "default", "high_speed";
248 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>;
249 pinctrl-1 = <&spi2_clk_hs &spi2_csn0 &spi2_miso_hs &spi2_mosi_hs>;
254 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
257 #address-cells = <1>;
258 #size-cells = <0>;
260 clock-names = "spiclk", "apb_pclk";
261 pinctrl-names = "default", "high_speed";
262 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>;
263 pinctrl-1 = <&spi2_clk_hs &spi2_csn0 &spi2_miso_hs &spi2_mosi_hs>;
268 compatible = "rockchip,rk3308-vop";
270 reg-names = "regs", "gamma_lut";
274 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
278 #address-cells = <1>;
279 #size-cells = <0>;
283 remote-endpoint = <&rgb_in_vop>;
289 compatible = "rockchip,rk3308-crypto";
291 clock-names = "sclk_crypto", "apkclk_crypto";
293 clock-frequency = <200000000>, <300000000>;
298 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
300 #pwm-cells = <3>;
301 pinctrl-names = "active";
302 pinctrl-0 = <&pwm0_pin>;
304 clock-names = "pwm", "pclk";
309 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
311 #pwm-cells = <3>;
312 pinctrl-names = "active";
313 pinctrl-0 = <&pwm1_pin>;
315 clock-names = "pwm", "pclk";
320 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
322 #pwm-cells = <3>;
323 pinctrl-names = "active";
324 pinctrl-0 = <&pwm2_pin>;
326 clock-names = "pwm", "pclk";
331 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
333 #pwm-cells = <3>;
334 pinctrl-names = "active";
335 pinctrl-0 = <&pwm3_pin>;
337 clock-names = "pwm", "pclk";
342 compatible = "rockchip,rk3308-rgb";
344 pinctrl-names = "default";
345 pinctrl-0 = <&lcdc_ctl>;
348 #address-cells = <1>;
349 #size-cells = <0>;
354 #address-cells = <1>;
355 #size-cells = <0>;
359 remote-endpoint = <&vop_out_rgb>;
367 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc";
370 #io-channel-cells = <1>;
372 clock-names = "saradc", "apb_pclk";
374 reset-names = "saradc-apb";
379 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
384 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
389 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
394 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
399 compatible = "rockchip,rk3308-vad", "rockchip,vad";
401 reg-names = "vad", "vad-memory";
403 rockchip,audio-src = <0>;
404 rockchip,audio-chnl-num = <8>;
405 rockchip,audio-chnl = <0>;
410 compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb",
415 clock-names = "otg";
417 g-np-tx-fifo-size = <16>;
418 g-rx-fifo-size = <275>;
419 g-tx-fifo-size = <256 128 128 64 64 32>;
420 g-use-dma;
422 phy-names = "usb2-phy";
427 compatible = "generic-ehci";
432 clock-names = "usbhost", "arbiter", "utmi";
434 phy-names = "usb";
439 compatible = "generic-ohci";
444 clock-names = "usbhost", "arbiter", "utmi";
446 phy-names = "usb";
450 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
452 max-frequency = <150000000>;
453 bus-width = <4>;
456 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
457 fifo-depth = <0x100>;
459 pinctrl-names = "default";
460 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
465 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
467 max-frequency = <150000000>;
468 bus-width = <8>;
471 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
472 fifo-depth = <0x100>;
478 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
480 max-frequency = <150000000>;
481 bus-width = <4>;
484 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
485 fifo-depth = <0x100>;
487 pinctrl-names = "default";
488 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
493 compatible = "rockchip,rk-nandc";
498 clock-names = "clk_nandc", "hclk_nandc";
508 clock-names = "clk_sfc", "hclk_sfc";
513 compatible = "rockchip,rk3308-mac";
517 interrupt-names = "macirq";
522 clock-names = "stmmaceth", "mac_clk_rx",
526 phy-mode = "rmii";
527 pinctrl-names = "default";
528 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
530 reset-names = "stmmaceth";
534 cru: clock-controller@ff500000 {
535 compatible = "rockchip,rk3308-cru";
538 #clock-cells = <1>;
539 #reset-cells = <1>;
542 gic: interrupt-controller@ff580000 {
543 compatible = "arm,gic-400";
544 #interrupt-cells = <3>;
545 #address-cells = <0>;
546 interrupt-controller;
556 compatible = "rockchip,rk3308-pinctrl";
558 #address-cells = <2>;
559 #size-cells = <2>;
563 compatible = "rockchip,gpio-bank";
568 gpio-controller;
569 #gpio-cells = <2>;
571 interrupt-controller;
572 #interrupt-cells = <2>;
576 compatible = "rockchip,gpio-bank";
581 gpio-controller;
582 #gpio-cells = <2>;
584 interrupt-controller;
585 #interrupt-cells = <2>;
589 compatible = "rockchip,gpio-bank";
594 gpio-controller;
595 #gpio-cells = <2>;
597 interrupt-controller;
598 #interrupt-cells = <2>;
602 compatible = "rockchip,gpio-bank";
607 gpio-controller;
608 #gpio-cells = <2>;
610 interrupt-controller;
611 #interrupt-cells = <2>;
615 compatible = "rockchip,gpio-bank";
620 gpio-controller;
621 #gpio-cells = <2>;
623 interrupt-controller;
624 #interrupt-cells = <2>;
627 pcfg_pull_up: pcfg-pull-up {
628 bias-pull-up;
631 pcfg_pull_down: pcfg-pull-down {
632 bias-pull-down;
635 pcfg_pull_none: pcfg-pull-none {
636 bias-disable;
639 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
640 bias-disable;
641 drive-strength = <2>;
644 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
645 bias-pull-up;
646 drive-strength = <2>;
649 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
650 bias-pull-up;
651 drive-strength = <4>;
654 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
655 bias-disable;
656 drive-strength = <4>;
659 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
660 bias-pull-down;
661 drive-strength = <4>;
664 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
665 bias-disable;
666 drive-strength = <8>;
669 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
670 bias-pull-up;
671 drive-strength = <8>;
674 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
675 bias-disable;
676 drive-strength = <12>;
679 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
680 bias-pull-up;
681 drive-strength = <12>;
684 pcfg_pull_none_smt: pcfg-pull-none-smt {
685 bias-disable;
686 input-schmitt-enable;
689 pcfg_output_high: pcfg-output-high {
690 output-high;
693 pcfg_output_low: pcfg-output-low {
694 output-low;
697 pcfg_input_high: pcfg-input-high {
698 bias-pull-up;
699 input-enable;
702 pcfg_input: pcfg-input {
703 input-enable;
707 i2c0_xfer: i2c0-xfer {
715 i2c1_xfer: i2c1-xfer {
723 i2c2_xfer: i2c2-xfer {
730 i2c3-m0 {
731 i2c3m0_xfer: i2c3m0-xfer {
738 i2c3-m1 {
739 i2c3m1_xfer: i2c3m1-xfer {
747 tsadc_otp_gpio: tsadc-otp-gpio {
752 tsadc_otp_out: tsadc-otp-out {
759 uart0_xfer: uart0-xfer {
765 uart0_cts: uart0-cts {
770 uart0_rts: uart0-rts {
777 uart1_xfer: uart1-xfer {
783 uart1_cts: uart1-cts {
788 uart1_rts: uart1-rts {
794 uart2-m0 {
795 uart2m0_xfer: uart2m0-xfer {
802 uart2-m1 {
803 uart2m1_xfer: uart2m1-xfer {
811 uart3_xfer: uart3-xfer {
820 uart4_xfer: uart4-xfer {
826 uart4_cts: uart4-cts {
832 uart4_rts: uart4-rts {
839 spi0_clk: spi0-clk {
844 spi0_csn0: spi0-csn0 {
849 spi0_miso: spi0-miso {
854 spi0_mosi: spi0-mosi {
858 spi0_clk_hs: spi0-clk-hs {
863 spi0_miso_hs: spi0-miso-hs {
868 spi0_mosi_hs: spi0-mosi-hs {
875 spi1_clk: spi1-clk {
880 spi1_csn0: spi1-csn0 {
885 spi1_miso: spi1-miso {
890 spi1_mosi: spi1-mosi {
894 spi1_clk_hs: spi1-clk-hs {
899 spi1_miso_hs: spi1-miso-hs {
904 spi1_mosi_hs: spi1-mosi-hs {
911 spi2_clk: spi2-clk {
916 spi2_csn0: spi2-csn0 {
921 spi2_miso: spi2-miso {
926 spi2_mosi: spi2-mosi {
930 spi2_clk_hs: spi2-clk-hs {
935 spi2_miso_hs: spi2-miso-hs {
940 spi2_mosi_hs: spi2-mosi-hs {
947 sdmmc_clk: sdmmc-clk {
952 sdmmc_cmd: sdmmc-cmd {
957 sdmmc_pwren: sdmmc-pwren {
962 sdmmc_bus1: sdmmc-bus1 {
967 sdmmc_bus4: sdmmc-bus4 {
975 sdmmc_gpio: sdmmc-gpio {
988 sdio_clk: sdio-clk {
993 sdio_cmd: sdio-cmd {
998 sdio_pwren: sdio-pwren {
1003 sdio_wrpt: sdio-wrpt {
1008 sdio_intn: sdio-intn {
1013 sdio_bus1: sdio-bus1 {
1018 sdio_bus4: sdio-bus4 {
1026 sdio_gpio: sdio-gpio {
1038 emmc_clk: emmc-clk {
1043 emmc_cmd: emmc-cmd {
1048 emmc_pwren: emmc-pwren {
1053 emmc_rstn: emmc-rstn {
1058 emmc_bus1: emmc-bus1 {
1063 emmc_bus4: emmc-bus4 {
1071 emmc_bus8: emmc-bus8 {
1085 flash_csn0: flash-csn0 {
1090 flash_rdy: flash-rdy {
1095 flash_ale: flash-ale {
1100 flash_cle: flash-cle {
1105 flash_wrn: flash-wrn {
1110 flash_rdn: flash-rdn {
1115 flash_bus8: flash-bus8 {
1129 pwm0_pin: pwm0-pin {
1136 pwm1_pin: pwm1-pin {
1143 pwm2_pin: pwm2-pin {
1150 pwm3_pin: pwm3-pin {
1157 rmii_pins: rmii-pins {
1179 mac_refclk_12ma: mac-refclk-12ma {
1184 mac_refclk: mac-refclk {
1192 lcdc_ctl: lcdc-ctl {