Lines Matching +full:0 +full:xff4b0000
35 #size-cells = <0>;
37 cpu0: cpu@0 {
40 reg = <0x0 0x0>;
47 reg = <0x0 0x1>;
54 reg = <0x0 0x2>;
61 reg = <0x0 0x3>;
79 #clock-cells = <0>;
101 reg = <0x0 0xff010000 0x0 0x10000>;
121 #clock-cells = <0>;
129 reg = <0x0 0xff000000 0x0 0x10000>;
135 reg = <0x0 0xff008000 0x0 0x4000>;
142 reg = <0x100 0x10>;
145 #clock-cells = <0>;
152 #phy-cells = <0>;
159 #phy-cells = <0>;
172 reg = <0x0 0xff0a0000 0x0 0x100>;
183 reg = <0x0 0xff0b0000 0x0 0x100>;
194 reg = <0x0 0xff0c0000 0x0 0x100>;
205 reg = <0x0 0xff0d0000 0x0 0x100>;
216 reg = <0x0 0xff0e0000 0x0 0x100>;
227 reg = <0x0 0xff120000 0x0 0x1000>;
230 #size-cells = <0>;
234 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>;
241 reg = <0x0 0xff130000 0x0 0x1000>;
244 #size-cells = <0>;
248 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>;
255 reg = <0x0 0xff140000 0x0 0x1000>;
258 #size-cells = <0>;
262 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>;
269 reg = <0x0 0xff2e0000 0x0 0x1fc>, <0x0 0xff2e0a00 0x0 0x400>;
279 #size-cells = <0>;
281 vop_out_rgb: endpoint@0 {
282 reg = <0>;
290 reg = <0x0 0xff2f0000 0x0 0x4000>;
299 reg = <0x0 0xff180000 0x0 0x10>;
302 pinctrl-0 = <&pwm0_pin>;
310 reg = <0x0 0xff180010 0x0 0x10>;
313 pinctrl-0 = <&pwm1_pin>;
321 reg = <0x0 0xff180020 0x0 0x10>;
324 pinctrl-0 = <&pwm2_pin>;
332 reg = <0x0 0xff180030 0x0 0x10>;
335 pinctrl-0 = <&pwm3_pin>;
345 pinctrl-0 = <&lcdc_ctl>;
349 #size-cells = <0>;
351 port@0 {
352 reg = <0>;
355 #size-cells = <0>;
357 rgb_in_vop: endpoint@0 {
358 reg = <0>;
368 reg = <0x0 0xff1e0000 0x0 0x100>;
380 reg = <0x0 0xff300000 0x0 0x10000>;
385 reg = <0x0 0xff100000 0x0 0x10000>;
390 reg = <0x0 0xff320000 0x0 0x10000>;
395 reg = <0x0 0xff330000 0x0 0x10000>;
400 reg = <0x0 0xff3c0000 0x0 0x10000>, <0x0 0xfff88000 0x0 0x38000>;
403 rockchip,audio-src = <0>;
405 rockchip,audio-chnl = <0>;
406 rockchip,mode = <0>;
412 reg = <0x0 0xff400000 0x0 0x40000>;
428 reg = <0x0 0xff440000 0x0 0x10000>;
440 reg = <0x0 0xff450000 0x0 0x10000>;
451 reg = <0x0 0xff480000 0x0 0x4000>;
457 fifo-depth = <0x100>;
460 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
466 reg = <0x0 0xff490000 0x0 0x4000>;
472 fifo-depth = <0x100>;
479 reg = <0x0 0xff4a0000 0x0 0x4000>;
485 fifo-depth = <0x100>;
488 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
494 reg = <0x0 0xff4b0000 0x0 0x4000>;
496 nandc_id = <0>;
505 reg = <0x0 0xff4c0000 0x0 0x4000>;
514 reg = <0x0 0xff4e0000 0x0 0x10000>;
528 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
536 reg = <0x0 0xff500000 0x0 0x1000>;
545 #address-cells = <0>;
548 reg = <0x0 0xff581000 0x0 0x1000>,
549 <0x0 0xff582000 0x0 0x2000>,
550 <0x0 0xff584000 0x0 0x2000>,
551 <0x0 0xff586000 0x0 0x2000>;
564 reg = <0x0 0xff220000 0x0 0x100>;
577 reg = <0x0 0xff230000 0x0 0x100>;
590 reg = <0x0 0xff240000 0x0 0x100>;
603 reg = <0x0 0xff250000 0x0 0x100>;
616 reg = <0x0 0xff260000 0x0 0x100>;
717 <0 RK_PB3 1 &pcfg_pull_none_smt>,
718 <0 RK_PB4 1 &pcfg_pull_none_smt>;
733 <0 RK_PB7 2 &pcfg_pull_none_smt>,
734 <0 RK_PC0 2 &pcfg_pull_none_smt>;
749 <0 RK_PB2 0 &pcfg_pull_none>;
754 <0 RK_PB2 1 &pcfg_pull_none>;
977 <4 RK_PD0 0 &pcfg_pull_up_4ma>,
978 <4 RK_PD1 0 &pcfg_pull_up_4ma>,
979 <4 RK_PD2 0 &pcfg_pull_up_4ma>,
980 <4 RK_PD3 0 &pcfg_pull_up_4ma>,
981 <4 RK_PD4 0 &pcfg_pull_up_4ma>,
982 <4 RK_PD5 0 &pcfg_pull_up_4ma>,
983 <4 RK_PD6 0 &pcfg_pull_up_4ma>;
1000 <0 RK_PA2 1 &pcfg_pull_none_8ma>;
1005 <0 RK_PA1 1 &pcfg_pull_none_8ma>;
1010 <0 RK_PA0 1 &pcfg_pull_none_8ma>;
1028 <4 RK_PA0 0 &pcfg_pull_up_4ma>,
1029 <4 RK_PA1 0 &pcfg_pull_up_4ma>,
1030 <4 RK_PA2 0 &pcfg_pull_up_4ma>,
1031 <4 RK_PA3 0 &pcfg_pull_up_4ma>,
1032 <4 RK_PA4 0 &pcfg_pull_up_4ma>,
1033 <4 RK_PA5 0 &pcfg_pull_up_4ma>;
1131 <0 RK_PB5 1 &pcfg_pull_none>;
1138 <0 RK_PB6 1 &pcfg_pull_none>;
1145 <0 RK_PB7 1 &pcfg_pull_none>;
1152 <0 RK_PC0 1 &pcfg_pull_none>;