Lines Matching +full:regulator +full:- +full:initial +full:- +full:mode
4 * SPDX-License-Identifier: GPL-2.0+ X11
7 /dts-v1/;
10 #include "rk322x-u-boot.dtsi"
11 #include <dt-bindings/input/input.h>
15 compatible = "rockchip,rk3229-gva", "rockchip,rk3229";
18 stdout-path = &uart2;
26 sdio_pwrseq: sdio-pwrseq {
27 compatible = "mmc-pwrseq-simple";
29 clock-names = "ext_clock";
30 pinctrl-names = "default";
31 pinctrl-0 = <&wifi_enable_h>;
36 * - SDIO_RESET_L_WL_REG_ON
37 * - PDN (power down when low)
39 reset-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; /* GPIO2_D2 */
42 vcc_host: vcc-host-regulator {
43 compatible = "regulator-fixed";
44 enable-active-high;
46 pinctrl-names = "default";
47 pinctrl-0 = <&host_vbus_drv>;
48 regulator-name = "vcc_host";
49 regulator-always-on;
50 regulator-boot-on;
53 wireless-bluetooth {
54 compatible = "bluetooth-platdata";
56 clock-names = "ext_clock";
58 pinctrl-names = "default", "rts_gpio";
65 wireless-wlan {
66 compatible = "wlan-platdata";
74 compatible = "gpio-keys";
75 #address-cells = <1>;
76 #size-cells = <0>;
79 pinctrl-names = "default";
80 pinctrl-0 = <&pwr_key>;
82 power_key: power-key {
86 debounce-interval = <100>;
87 wakeup-source;
100 interrupt-parent = <&gpio1>;
102 pinctrl-names = "default";
103 pinctrl-0 = <&pmic_int_l>;
104 rockchip,system-power-controller;
105 wakeup-source;
106 gpio-controller;
107 #gpio-cells = <2>;
108 #clock-cells = <1>;
109 clock-output-names = "xin32k", "rk805-clkout2";
124 compatible = "rk805-regulator";
126 #address-cells = <1>;
127 #size-cells = <0>;
130 regulator-compatible = "RK805_DCDC1";
131 regulator-name = "vdd_arm";
132 regulator-min-microvolt = <712500>;
133 regulator-max-microvolt = <1450000>;
134 regulator-initial-mode = <0x1>;
135 regulator-ramp-delay = <12500>;
136 regulator-boot-on;
137 regulator-always-on;
138 regulator-state-mem {
139 regulator-mode = <0x2>;
140 regulator-on-in-suspend;
141 regulator-suspend-microvolt = <950000>;
146 regulator-compatible = "RK805_DCDC2";
147 regulator-name = "vdd_logic";
148 regulator-min-microvolt = <712500>;
149 regulator-max-microvolt = <1450000>;
150 regulator-initial-mode = <0x1>;
151 regulator-ramp-delay = <12500>;
152 regulator-boot-on;
153 regulator-always-on;
154 regulator-state-mem {
155 regulator-mode = <0x2>;
156 regulator-on-in-suspend;
157 regulator-suspend-microvolt = <1000000>;
162 regulator-compatible = "RK805_DCDC3";
163 regulator-name = "vcc_ddr";
164 regulator-initial-mode = <0x1>;
165 regulator-boot-on;
166 regulator-always-on;
167 regulator-state-mem {
168 regulator-mode = <0x2>;
169 regulator-on-in-suspend;
174 regulator-compatible = "RK805_DCDC4";
175 regulator-name = "vcc_io";
176 regulator-min-microvolt = <3300000>;
177 regulator-max-microvolt = <3300000>;
178 regulator-initial-mode = <0x1>;
179 regulator-boot-on;
180 regulator-always-on;
181 regulator-state-mem {
182 regulator-mode = <0x2>;
183 regulator-on-in-suspend;
184 regulator-suspend-microvolt = <3300000>;
189 regulator-compatible = "RK805_LDO1";
190 regulator-name = "vcc_18";
191 regulator-min-microvolt = <1800000>;
192 regulator-max-microvolt = <1800000>;
193 regulator-boot-on;
194 regulator-always-on;
195 regulator-state-mem {
196 regulator-on-in-suspend;
197 regulator-suspend-microvolt = <1800000>;
202 regulator-compatible = "RK805_LDO2";
203 regulator-name = "vcc_18emmc";
204 regulator-min-microvolt = <1800000>;
205 regulator-max-microvolt = <1800000>;
206 regulator-boot-on;
207 regulator-always-on;
208 regulator-state-mem {
209 regulator-on-in-suspend;
210 regulator-suspend-microvolt = <1800000>;
215 regulator-compatible = "RK805_LDO3";
216 regulator-name = "vdd_10";
217 regulator-min-microvolt = <1000000>;
218 regulator-max-microvolt = <1000000>;
219 regulator-boot-on;
220 regulator-always-on;
221 regulator-state-mem {
222 regulator-on-in-suspend;
223 regulator-suspend-microvolt = <1000000>;
251 cpu-supply = <&vdd_arm>;
256 pmic_int_l: pmic-int-l {
261 sdio-pwrseq {
262 wifi_enable_h: wifi-enable-h {
268 host_vbus_drv: host-vbus-drv {
274 pwr_key: pwr-key {
281 rockchip,pctl-timing = <0x96 0xC8 0x1F3 0xF 0x8000004D 0x4 0x4E 0x6 0x3
286 rockchip,phy-timing = <0x220 0x1 0x0 0x0 0x0 0x4 0x60>;
287 rockchip,sdram-params = <0x428B188 0x0 0x21 0x472 0x15
302 u2phy0_otg: otg-port {
306 u2phy0_host: host-port {