Lines Matching +full:saradc +full:- +full:apb
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/clock/rk3128-cru.h>
12 #include <dt-bindings/media/rockchip_mipi_dsi.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <1>;
20 #size-cells = <1>;
44 arm-pmu {
45 compatible = "arm,cortex-a7-pmu";
53 #address-cells = <1>;
54 #size-cells = <0>;
55 enable-method = "rockchip,rk3128-smp";
59 compatible = "arm,cortex-a7";
61 operating-points = <
65 #cooling-cells = <2>; /* min followed by max */
66 clock-latency = <40000>;
72 compatible = "arm,cortex-a7";
78 compatible = "arm,cortex-a7";
84 compatible = "arm,cortex-a7";
91 #address-cells = <1>;
92 #size-cells = <1>;
96 #address-cells = <1>;
97 #size-cells = <1>;
143 #address-cells = <1>;
144 #size-cells = <1>;
149 rockchip,read-latency = <0x3f>;
155 compatible = "arm,psci-1.0";
160 compatible = "arm,amba-bus";
161 #address-cells = <1>;
162 #size-cells = <1>;
163 interrupt-parent = <&gic>;
169 arm,pl330-broken-no-flushp;//2
172 #dma-cells = <1>;
174 clock-names = "apb_pclk";
179 compatible = "fixed-clock";
180 clock-frequency = <24000000>;
181 clock-output-names = "xin24m";
182 #clock-cells = <0>;
186 compatible = "fixed-clock";
188 clock-frequency = <12000000>;
189 clock-output-names = "xin12m";
190 #clock-cells = <0>;
195 compatible = "arm,armv7-timer";
196 arm,cpu-registers-not-fw-configured;
199 clock-frequency = <24000000>;
203 compatible = "arm,armv7-timer";
212 clock-names = "pclk_wdt";
223 #reset-cells = <1>;
231 clock-names = "clk_sfc", "hclk_sfc";
232 assigned-clocks = <&cru SCLK_SFC>;
233 assigned-clock-rates = <60000000>;
238 compatible = "rockchip,rk-nandc";
243 clock-names = "clk_nandc", "hclk_nandc";
248 compatible = "rockchip,rk3128-dmc", "syscon";
252 cru: clock-controller@20000000 {
253 compatible = "rockchip,rk3128-cru";
256 #clock-cells = <1>;
257 #reset-cells = <1>;
258 assigned-clocks = <&cru PLL_GPLL>;
259 assigned-clock-rates = <594000000>;
263 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
266 reg-shift = <2>;
267 reg-io-width = <4>;
268 clock-frequency = <24000000>;
270 clock-names = "baudclk", "apb_pclk";
271 pinctrl-names = "default";
272 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
274 #dma-cells = <2>;
278 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
281 reg-shift = <2>;
282 reg-io-width = <4>;
283 clock-frequency = <24000000>;
285 clock-names = "baudclk", "apb_pclk";
286 pinctrl-names = "default";
287 pinctrl-0 = <&uart1_xfer>;
289 #dma-cells = <2>;
293 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
296 reg-shift = <2>;
297 reg-io-width = <4>;
298 clock-frequency = <24000000>;
300 clock-names = "baudclk", "apb_pclk";
301 pinctrl-names = "default";
302 pinctrl-0 = <&uart2_xfer>;
304 #dma-cells = <2>;
307 saradc: saradc@2006c000 { label
308 compatible = "rockchip,saradc";
311 #io-channel-cells = <1>;
313 clock-names = "saradc", "apb_pclk";
315 reset-names = "saradc-apb";
320 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
322 #pwm-cells = <3>;
323 pinctrl-names = "active";
324 pinctrl-0 = <&pwm0_pin>;
326 clock-names = "pwm";
330 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
332 #pwm-cells = <2>;
333 pinctrl-names = "active";
334 pinctrl-0 = <&pwm1_pin>;
336 clock-names = "pwm";
340 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
342 #pwm-cells = <2>;
343 pinctrl-names = "active";
344 pinctrl-0 = <&pwm2_pin>;
346 clock-names = "pwm";
350 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
352 #pwm-cells = <2>;
353 pinctrl-names = "active";
354 pinctrl-0 = <&pwm3_pin>;
356 clock-names = "pwm";
360 compatible = "rockchip,rk3128-smp-sram", "mmio-sram";
362 map-exec;
363 map-cacheable;
367 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
369 #address-cells = <1>;
370 #size-cells = <1>;
374 compatible = "rockchip,rk3126-vop";
376 reg-names = "regs", "gamma_lut";
379 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
383 #address-cells = <1>;
384 #size-cells = <0>;
388 remote-endpoint = <&lvds_in_vop>;
393 remote-endpoint = <&dsi_in_vop>;
398 remote-endpoint = <&rgb_in_vop>;
404 compatible = "rockchip,rk3128-mipi-dsi";
408 clock-names = "pclk", "h2p", "hs_clk";
410 reset-names = "apb";
412 phy-names = "mipi_dphy";
414 #address-cells = <1>;
415 #size-cells = <0>;
421 remote-endpoint = <&vop_out_dsi>;
427 display_subsystem: display-subsystem {
428 compatible = "rockchip,display-subsystem";
432 route_lvds: route-lvds {
440 route_dsi: route-dsi {
450 gic: interrupt-controller@10139000 {
451 compatible = "arm,gic-400";
452 interrupt-controller;
453 #interrupt-cells = <3>;
454 #address-cells = <0>;
463 compatible = "rockchip,rk3128-usb", "rockchip,rk3288-usb",
468 g-use-dma;
469 hnp-srp-disable;
471 phy-names = "usb";
476 compatible = "generic-ehci";
480 phy-names = "usb";
485 compatible = "generic-ohci";
489 phy-names = "usb";
494 compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc";
496 max-frequency = <150000000>;
500 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
501 fifo-depth = <0x100>;
502 pinctrl-names = "default";
503 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
504 bus-width = <4>;
509 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
511 max-frequency = <150000000>;
515 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
516 bus-width = <8>;
517 default-sample-phase = <158>;
518 num-slots = <1>;
519 fifo-depth = <0x100>;
520 pinctrl-names = "default";
521 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
523 reset-names = "reset";
527 video_phy: video-phy@20038000 {
528 compatible = "rockchip,rk3128-video-phy";
532 clock-names = "ref", "pclk_phy", "pclk_host";
533 #clock-cells = <0>;
535 reset-names = "rst";
536 #phy-cells = <0>;
541 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
544 #address-cells = <1>;
545 #size-cells = <0>;
546 clock-names = "i2c";
548 pinctrl-names = "default";
549 pinctrl-0 = <&i2c0_xfer>;
553 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
556 #address-cells = <1>;
557 #size-cells = <0>;
558 clock-names = "i2c";
560 pinctrl-names = "default";
561 pinctrl-0 = <&i2c1_xfer>;
565 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
568 #address-cells = <1>;
569 #size-cells = <0>;
570 clock-names = "i2c";
572 pinctrl-names = "default";
573 pinctrl-0 = <&i2c2_xfer>;
577 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
580 #address-cells = <1>;
581 #size-cells = <0>;
582 clock-names = "i2c";
584 pinctrl-names = "default";
585 pinctrl-0 = <&i2c3_xfer>;
589 compatible = "rockchip,rk3128-spi", "rockchip,rk3288-spi";
592 pinctrl-names = "default";
593 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>;
594 clock-names = "spiclk", "apb_pclk";
596 dma-names = "tx", "rx";
597 #address-cells = <1>;
598 #size-cells = <0>;
603 compatible = "rockchip,rk3128-grf", "syscon";
605 #address-cells = <1>;
606 #size-cells = <1>;
609 compatible = "rockchip,rk3126-lvds";
611 phy-names = "phy";
615 #address-cells = <1>;
616 #size-cells = <0>;
622 remote-endpoint = <&vop_out_lvds>;
629 compatible = "rockchip,rk3128-rgb";
631 phy-names = "phy";
632 pinctrl-names = "default", "sleep";
633 pinctrl-0 = <&lcdc_rgb_pins>;
634 pinctrl-1 = <&lcdc_sleep_pins>;
638 #address-cells = <1>;
639 #size-cells = <0>;
645 remote-endpoint = <&vop_out_rgb>;
651 u2phy: usb2-phy@17c {
652 compatible = "rockchip,rk3128-usb2phy";
655 clock-names = "phyclk";
656 #clock-cells = <0>;
657 clock-output-names = "usb480m_phy";
658 assigned-clocks = <&cru SCLK_USB480M>;
659 assigned-clock-parents = <&u2phy>;
662 u2phy_otg: otg-port {
663 #phy-cells = <0>;
667 interrupt-names = "otg-bvalid", "otg-id",
672 u2phy_host: host-port {
673 #phy-cells = <0>;
675 interrupt-names = "linestate";
682 compatible = "rockchip,rk3128-pinctrl";
687 reg-names = "base", "mux", "pull", "drv";
689 #address-cells = <1>;
690 #size-cells = <1>;
694 compatible = "rockchip,gpio-bank";
698 gpio-controller;
699 #gpio-cells = <2>;
700 interrupt-controller;
701 #interrupt-cells = <2>;
705 compatible = "rockchip,gpio-bank";
709 gpio-controller;
710 #gpio-cells = <2>;
711 interrupt-controller;
712 #interrupt-cells = <2>;
716 compatible = "rockchip,gpio-bank";
720 gpio-controller;
721 #gpio-cells = <2>;
722 interrupt-controller;
723 #interrupt-cells = <2>;
727 compatible = "rockchip,gpio-bank";
731 gpio-controller;
732 #gpio-cells = <2>;
733 interrupt-controller;
734 #interrupt-cells = <2>;
738 bias-pull-pin-default;
741 pcfg_pull_none: pcfg-pull-none {
742 bias-disable;
746 emmc_clk: emmc-clk {
750 emmc_cmd: emmc-cmd {
754 emmc_cmd1: emmc-cmd1 {
758 emmc_pwr: emmc-pwr {
762 emmc_bus1: emmc-bus1 {
766 emmc_bus4: emmc-bus4 {
773 emmc_bus8: emmc-bus8 {
786 i2c0_xfer: i2c0-xfer {
793 i2c1_xfer: i2c1-xfer {
800 i2c2_xfer: i2c2-xfer {
807 i2c3_xfer: i2c3-xfer {
814 lcdc_rgb_pins: lcdc-rgb-pins {
836 lcdc_sleep_pins: lcdc-sleep-pins {
860 uart0_xfer: uart0-xfer {
865 uart0_cts: uart0-cts {
869 uart0_rts: uart0-rts {
875 uart1_xfer: uart1-xfer {
880 uart1_cts: uart1-cts {
884 uart1_rts: uart1-rts {
890 uart2_xfer: uart2-xfer {
895 uart2_cts: uart2-cts {
899 uart2_rts: uart2-rts {
905 sdmmc_clk: sdmmc-clk {
909 sdmmc_cmd: sdmmc-cmd {
913 sdmmc_wp: sdmmc-wp {
917 sdmmc_pwren: sdmmc-pwren {
921 sdmmc_bus4: sdmmc-bus4 {
930 sdio_clk: sdio-clk {
934 sdio_cmd: sdio-cmd {
938 sdio_pwren: sdio-pwren {
942 sdio_bus4: sdio-bus4 {
951 hdmii2c_xfer: hdmii2c-xfer {
958 i2s_bus: i2s-bus {
967 i2s1_bus: i2s1-bus {
978 pwm0_pin: pwm0-pin {
984 pwm1_pin: pwm1-pin {
990 pwm2_pin: pwm2-pin {
996 pwm3_pin: pwm3-pin {
1002 rgmii_pins: rgmii-pins {
1020 rmii_pins: rmii-pins {
1035 spdif_tx: spdif-tx {
1041 spi0_clk: spi0-clk {
1045 spi0_cs0: spi0-cs0 {
1049 spi0_tx: spi0-tx {
1053 spi0_rx: spi0-rx {
1057 spi0_cs1: spi0-cs1 {
1061 spi1_clk: spi1-clk {
1065 spi1_cs0: spi1-cs0 {
1069 spi1_tx: spi1-tx {
1073 spi1_rx: spi1-rx {
1077 spi1_cs1: spi1-cs1 {
1081 spi2_clk: spi2-clk {
1085 spi2_cs0: spi2-cs0 {
1089 spi2_tx: spi2-tx {
1093 spi2_rx: spi2-rx {