Lines Matching +full:0 +full:x10180000
41 reg = <0x60000000 0x40000000>;
54 #size-cells = <0>;
57 cpu0:cpu@0x000 {
60 reg = <0x000>;
70 cpu1:cpu@0x001 {
73 reg = <0x001>;
76 cpu2:cpu@0x002 {
79 reg = <0x002>;
82 cpu3:cpu@0x003 {
85 reg = <0x003>;
101 reg = <0x10128080 0x20>;
105 reg = <0x1012a000 0x20>;
109 reg = <0x1012c000 0x20>;
113 reg = <0x1012d000 0x20>;
117 reg = <0x1012e000 0x20>;
121 reg = <0x1012f000 0x20>;
124 reg = <0x1012f080 0x20>;
128 reg = <0x1012f100 0x20>;
132 reg = <0x1012f180 0x20>;
137 reg = <0x1012f200 0x20>;
148 reg = <0x10128000 0x20>;
149 rockchip,read-latency = <0x3f>;
168 reg = <0x20078000 0x4000>;
170 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
182 #clock-cells = <0>;
190 #clock-cells = <0>;
204 reg = <0x20044000 0xb8>;
211 reg = <0x2004c000 0x100>;
217 rockchip,debug = <0>;
222 reg = <0x20000110 0x24>;
228 reg = <0x1020c000 0x8000>;
239 reg = <0x10500000 0x4000>;
241 nandc_id = <0>;
249 reg = <0x0 0x20004000 0x0 0x1000>;
254 reg = <0x20000000 0x1000>;
264 reg = <0x20060000 0x100>;
272 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
279 reg = <0x20064000 0x100>;
287 pinctrl-0 = <&uart1_xfer>;
294 reg = <0x20068000 0x100>;
302 pinctrl-0 = <&uart2_xfer>;
309 reg = <0x2006c000 0x100>;
321 reg = <0x20050000 0x10>;
324 pinctrl-0 = <&pwm0_pin>;
331 reg = <0x20050010 0x10>;
334 pinctrl-0 = <&pwm1_pin>;
341 reg = <0x20050020 0x10>;
344 pinctrl-0 = <&pwm2_pin>;
351 reg = <0x20050030 0x10>;
354 pinctrl-0 = <&pwm3_pin>;
361 reg = <0x10080400 0x1C00>;
368 reg = <0x100a0000 0x1000>;
375 reg = <0x1010e000 0x100>, <0x1010ec00 0x400>;
384 #size-cells = <0>;
386 vop_out_lvds: endpoint@0 {
387 reg = <0>;
405 reg = <0x10110000 0x4000>;
415 #size-cells = <0>;
454 #address-cells = <0>;
455 reg = <0x10139000 0x1000>,
456 <0x1013a000 0x1000>,
457 <0x1013c000 0x2000>,
458 <0x1013e000 0x2000>;
459 interrupts = <GIC_PPI 9 0xf04>;
465 reg = <0x10180000 0x40000>;
477 reg = <0x101c0000 0x20000>;
486 reg = <0x101e0000 0x20000>;
495 reg = <0x10214000 0x4000>;
501 fifo-depth = <0x100>;
503 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
510 reg = <0x1021c000 0x4000>;
519 fifo-depth = <0x100>;
521 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
529 reg = <0x20038000 0x4000>, <0x10110000 0x4000>;
533 #clock-cells = <0>;
536 #phy-cells = <0>;
542 reg = <0x20072000 0x1000>;
545 #size-cells = <0>;
549 pinctrl-0 = <&i2c0_xfer>;
554 reg = <0x20056000 0x1000>;
557 #size-cells = <0>;
561 pinctrl-0 = <&i2c1_xfer>;
566 reg = <0x2005a000 0x1000>;
569 #size-cells = <0>;
573 pinctrl-0 = <&i2c2_xfer>;
578 reg = <0x2005e000 0x1000>;
581 #size-cells = <0>;
585 pinctrl-0 = <&i2c3_xfer>;
590 reg = <0x20074000 0x1000>;
593 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>;
598 #size-cells = <0>;
604 reg = <0x20008000 0x1000>;
616 #size-cells = <0>;
618 port@0 {
619 reg = <0>;
633 pinctrl-0 = <&lcdc_rgb_pins>;
639 #size-cells = <0>;
641 port@0 {
642 reg = <0>;
653 reg = <0x017c 0x0c>;
656 #clock-cells = <0>;
663 #phy-cells = <0>;
673 #phy-cells = <0>;
683 reg = <0x20008000 0xA8>,
684 <0x200080A8 0x4C>,
685 <0x20008118 0x20>,
686 <0x20008100 0x04>;
695 reg = <0x2007c000 0x100>;
706 reg = <0x20080000 0x100>;
717 reg = <0x20084000 0x100>;
728 reg = <0x20088000 0x100>;
787 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
788 <0 RK_PA1 1 &pcfg_pull_none>;
794 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
795 <0 RK_PA3 1 &pcfg_pull_none>;
808 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
809 <0 RK_PA7 1 &pcfg_pull_none>;
838 <2 RK_PB0 0 &pcfg_pull_none>, /* LCDC_DCLK */
839 <2 RK_PB1 0 &pcfg_pull_none>, /* LCDC_HSYNC */
840 <2 RK_PB2 0 &pcfg_pull_none>, /* LCDC_VSYNC */
841 <2 RK_PB3 0 &pcfg_pull_none>, /* LCDC_DEN */
842 <2 RK_PB4 0 &pcfg_pull_none>, /* LCDC_DATA10 */
843 <2 RK_PB5 0 &pcfg_pull_none>, /* LCDC_DATA11 */
844 <2 RK_PB6 0 &pcfg_pull_none>, /* LCDC_DATA12 */
845 <2 RK_PB7 0 &pcfg_pull_none>, /* LCDC_DATA13 */
846 <2 RK_PC0 0 &pcfg_pull_none>, /* LCDC_DATA14 */
847 <2 RK_PC1 0 &pcfg_pull_none>, /* LCDC_DATA15 */
848 <2 RK_PC2 0 &pcfg_pull_none>, /* LCDC_DATA16 */
849 <2 RK_PC3 0 &pcfg_pull_none>, /* LCDC_DATA17 */
850 <2 RK_PC4 0 &pcfg_pull_none>, /* LCDC_DATA18 */
851 <2 RK_PC5 0 &pcfg_pull_none>, /* LCDC_DATA19 */
852 <2 RK_PC6 0 &pcfg_pull_none>, /* LCDC_DATA20 */
853 <2 RK_PC7 0 &pcfg_pull_none>, /* LCDC_DATA21 */
854 <2 RK_PD0 0 &pcfg_pull_none>, /* LCDC_DATA22 */
855 <2 RK_PD1 0 &pcfg_pull_none>; /* LCDC_DATA23 */
870 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>;
896 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
900 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
935 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>;
939 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>;
952 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
953 <0 RK_PA7 2 &pcfg_pull_none>;
959 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
960 <0 RK_PB1 1 &pcfg_pull_none>,
961 <0 RK_PB3 1 &pcfg_pull_none>,
962 <0 RK_PB4 1 &pcfg_pull_none>,
963 <0 RK_PB5 1 &pcfg_pull_none>,
964 <0 RK_PB6 1 &pcfg_pull_none>;
979 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>;
985 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
991 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
1082 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>;
1086 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>;
1090 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>;
1094 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>;