arm/dts/px30.dtsi

34 		#size-cells = <0>;
36 		cpu0: cpu@0 {
39 			reg = <0x0 0x0>;
46 			reg = <0x0 0x1>;
52 			reg = <0x0 0x2>;
58 			reg = <0x0 0x3>;
74 		reg = <0x0 0xff2a0000 0x0 0x1000>;
94 		#clock-cells = <0>;
112 		#clock-cells = <0>;
119 		reg = <0x0 0xff000000 0x0 0x1000>;
125 			#size-cells = <0>;
195 		reg = <0x0 0xff010000 0x0 0x1000>;
206 			offset = <0x200>;
226 		reg = <0x0 0xff030000 0x0 0x100>;
232 		dmas = <&dmac 0>, <&dmac 1>;
235 		pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
241 		reg = <0x0 0xff060000 0x0 0x1000>;
252 		reg = <0x0 0xff070000 0x0 0x1000>;
263 		reg = <0x0 0xff080000 0x0 0x1000>;
274 		reg = <0x0 0xff0a0000 0x0 0x1000>;
284 		reg = <0x0 0xff0b0000 0x0 0x4000>;
294 		#address-cells = <0>;
296 		reg = <0x0 0xff131000 0 0x1000>,
297 		      <0x0 0xff132000 0 0x2000>,
298 		      <0x0 0xff134000 0 0x2000>,
299 		      <0x0 0xff136000 0 0x2000>;
306 		reg = <0x0 0xff140000 0x0 0x1000>;
323 				#size-cells = <0>;
325 				port@0 {
326 					reg = <0>;
328 					#size-cells = <0>;
330 					lvds_in_vopb: endpoint@0 {
331 						reg = <0>;
346 			pinctrl-0 = <&lcdc_m0_rgb_pins>;
352 				#size-cells = <0>;
354 				port@0 {
355 					reg = <0>;
357 					#size-cells = <0>;
359 					rgb_in_vopb: endpoint@0 {
360 						reg = <0>;
375 		reg = <0x0 0xff148000 0x0 0x1000>;
389 		reg = <0x0 0xff158000 0x0 0x100>;
398 		pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
404 		reg = <0x0 0xff160000 0x0 0x100>;
413 		pinctrl-0 = <&uart2m0_xfer>;
419 		reg = <0x0 0xff168000 0x0 0x100>;
428 		pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
434 		reg = <0x0 0xff170000 0x0 0x100>;
443 		pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
449 		reg = <0x0 0xff178000 0x0 0x100>;
458 		pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
464 		reg = <0x0 0xff180000 0x0 0x1000>;
469 		pinctrl-0 = <&i2c0_xfer>;
471 		#size-cells = <0>;
477 		reg = <0x0 0xff190000 0x0 0x1000>;
482 		pinctrl-0 = <&i2c1_xfer>;
484 		#size-cells = <0>;
490 		reg = <0x0 0xff1a0000 0x0 0x1000>;
495 		pinctrl-0 = <&i2c2_xfer>;
497 		#size-cells = <0>;
503 		reg = <0x0 0xff1b0000 0x0 0x1000>;
508 		pinctrl-0 = <&i2c3_xfer>;
510 		#size-cells = <0>;
516 		reg = <0x0 0xff1d0000 0x0 0x1000>;
519 		#size-cells = <0>;
526 		pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
532 		reg = <0x0 0xff1d8000 0x0 0x1000>;
535 		#size-cells = <0>;
542 		pinctrl-0 = <&spi1_clk &spi1_csn &spi1_miso &spi1_mosi>;
548 		reg = <0x0 0xff1e0000 0x0 0x100>;
555 		reg = <0x0 0xff200000 0x0 0x10>;
558 		pinctrl-0 = <&pwm0_pin>;
566 		reg = <0x0 0xff200010 0x0 0x10>;
569 		pinctrl-0 = <&pwm1_pin>;
577 		reg = <0x0 0xff200020 0x0 0x10>;
580 		pinctrl-0 = <&pwm2_pin>;
588 		reg = <0x0 0xff200030 0x0 0x10>;
591 		pinctrl-0 = <&pwm3_pin>;
599 		reg = <0x0 0xff208000 0x0 0x10>;
602 		pinctrl-0 = <&pwm4_pin>;
610 		reg = <0x0 0xff208010 0x0 0x10>;
613 		pinctrl-0 = <&pwm5_pin>;
621 		reg = <0x0 0xff208020 0x0 0x10>;
624 		pinctrl-0 = <&pwm6_pin>;
632 		reg = <0x0 0xff208030 0x0 0x10>;
635 		pinctrl-0 = <&pwm7_pin>;
649 			reg = <0x0 0xff240000 0x0 0x4000>;
661 		reg = <0x0 0xff280000 0x0 0x100>;
671 		pinctrl-0 = <&tsadc_otp_gpio>;
681 		reg = <0x0 0xff288000 0x0 0x100>;
693 		reg = <0x0 0xff2b0000 0x0 0x9000>;
710 		reg = <0x0 0xff2bc000 0x0 0x1000>;
730 		reg = <0x0 0xff2c0000 0x0 0x10000>;
737 			reg = <0x100 0x10>;
740 			#clock-cells = <0>;
747 				#phy-cells = <0>;
754 				#phy-cells = <0>;
767 		reg = <0x0 0xff2e0000 0x0 0x10000>,
768 		      <0x0 0xff450000 0x0 0x10000>;
772 		#clock-cells = <0>;
776 		#phy-cells = <0>;
783 		reg = <0x0 0xff300000 0x0 0x40000>;
799 		reg = <0x0 0xff340000 0x0 0x10000>;
811 		reg = <0x0 0xff350000 0x0 0x10000>;
822 		reg = <0x0 0xff360000 0x0 0x10000>;
836 		pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
845 		reg = <0x0 0xff370000 0x0 0x4000>;
850 		fifo-depth = <0x100>;
854 		pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
860 		reg = <0x0 0xff380000 0x0 0x4000>;
865 		fifo-depth = <0x100>;
872 		reg = <0x0 0xff390000 0x0 0x4000>;
877 		fifo-depth = <0x100>;
884 		reg = <0x0 0xff3a0000 0x0 0x4000>;
893 		reg = <0x0 0xff3b0000 0x0 0x4000>;
895 		nandc_id = <0>;
903 		reg = <0x0 0xff400000 0x0 0x4000>;
919 		reg = <0x0 0xff440000 0x0 0x400>;
931 		reg = <0x0 0xff442000 0x0 0x800>;
935 		dev_mode = <0>;
954 		mode_ctrl = <0x410>;
961 		reg = <0x0 0xff440440 0x0 0x40>, <0x0 0xff440480 0x0 0x40>;
966 		#iommu-cells = <0>;
971 		reg = <0x0 0xff442800 0x0 0x100>;
976 		#iommu-cells = <0>;
981 		reg = <0x0 0xff450000 0x0 0x10000>;
992 		#size-cells = <0>;
997 			#size-cells = <0>;
999 			port@0 {
1000 				reg = <0>;
1002 				#size-cells = <0>;
1004 				dsi_in_vopl: endpoint@0 {
1005 					reg = <0>;
1019 		reg = <0x0 0xff460000 0x0 0x1fc>, <0x0 0xff460a00 0x0 0x400>;
1030 			#size-cells = <0>;
1032 			vopb_out_lvds: endpoint@0 {
1033 				reg = <0>;
1051 		reg = <0x0 0xff460f00 0x0 0x100>;
1056 		#iommu-cells = <0>;
1062 		reg = <0x0 0xff470000 0x0 0x1fc>, <0x0 0xff470a00 0x0 0x400>;
1073 			#size-cells = <0>;
1075 			vopl_out_lvds: endpoint@0 {
1076 				reg = <0>;
1094 		reg = <0x0 0xff470f00 0x0 0x100>;
1099 		#iommu-cells = <0>;
1106 		reg = <0x0 0xff480000 0x0 0x1000>;
1116 		reg = <0x0 0xff490000 0x0 0x200>;
1123 		pinctrl-0 = <&dvp_d2d9_m0>;
1129 		reg = <0x0 0xff490800 0x0 0x100>;
1135 		#iommu-cells = <0>;
1141 		reg = <0x0 0xff4a0000 0x0 0x4000>;
1150 		pinctrl-0 = <&cif_clkout_m0>;
1151 		rockchip,isp,mipiphy = <0>;
1152 		rockchip,isp,csiphy,reg = <0xff2f0000 0x4000>;
1162 		reg = <0x0 0xff4a8000 0x0 0x100>;
1168 		#iommu-cells = <0>;
1174 		reg = <0x0 0xff518000 0x0 0x20>;
1179 		reg = <0x0 0xff520000 0x0 0x20>;
1184 		reg = <0x0 0xff52c000 0x0 0x20>;
1189 		reg = <0x0 0xff538000 0x0 0x20>;
1194 		reg = <0x0 0xff538080 0x0 0x20>;
1199 		reg = <0x0 0xff538100 0x0 0x20>;
1204 		reg = <0x0 0xff538180 0x0 0x20>;
1209 		reg = <0x0 0xff540000 0x0 0x20>;
1214 		reg = <0x0 0xff540080 0x0 0x20>;
1219 		reg = <0x0 0xff548000 0x0 0x20>;
1224 		reg = <0x0 0xff548080 0x0 0x20>;
1229 		reg = <0x0 0xff548100 0x0 0x20>;
1234 		reg = <0x0 0xff548180 0x0 0x20>;
1239 		reg = <0x0 0xff548200 0x0 0x20>;
1244 		reg = <0x0 0xff550000 0x0 0x20>;
1249 		reg = <0x0 0xff550080 0x0 0x20>;
1254 		reg = <0x0 0xff550100 0x0 0x20>;
1259 		reg = <0x0 0xff550180 0x0 0x20>;
1264 		reg = <0x0 0xff558000 0x0 0x20>;
1269 		reg = <0x0 0xff558080 0x0 0x20>;
1282 			reg = <0x0 0xff040000 0x0 0x100>;
1294 			reg = <0x0 0xff250000 0x0 0x100>;
1306 			reg = <0x0 0xff260000 0x0 0x100>;
1318 			reg = <0x0 0xff270000 0x0 0x100>;
1410 					<0 RK_PB0 RK_FUNC_1 &pcfg_pull_none_smt>,
1411 					<0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>;
1418 					<0 RK_PC2 RK_FUNC_1 &pcfg_pull_none_smt>,
1419 					<0 RK_PC3 RK_FUNC_1 &pcfg_pull_none_smt>;
1442 					<0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1447 					<0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
1454 					<0 RK_PB2 RK_FUNC_1 &pcfg_pull_up>,
1455 					<0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;
1460 					<0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>;
1465 					<0 RK_PB5 RK_FUNC_1 &pcfg_pull_none>;
1470 					<0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1516 					<0 RK_PC0 RK_FUNC_2 &pcfg_pull_up>,
1517 					<0 RK_PC1 RK_FUNC_2 &pcfg_pull_none>;
1522 					<0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
1527 					<0 RK_PC3 RK_FUNC_2 &pcfg_pull_none>;
1532 					<0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
1869 					<0 RK_PA3 RK_FUNC_1 &pcfg_pull_up_8ma>;
2096 					<0 RK_PB7 RK_FUNC_1 &pcfg_pull_none>;
2103 					<0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;
2117 					<0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>;