Lines Matching +full:vf610 +full:- +full:i2c
4 * Copyright 2013-2015 Freescale Semiconductor, Inc.
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
27 #address-cells = <1>;
28 #size-cells = <0>;
31 compatible = "arm,cortex-a7";
38 compatible = "arm,cortex-a7";
46 compatible = "arm,armv7-timer";
54 compatible = "arm,cortex-a7-pmu";
60 compatible = "simple-bus";
61 #address-cells = <1>;
62 #size-cells = <1>;
64 interrupt-parent = <&gic>;
67 gic: interrupt-controller@1400000 {
68 compatible = "arm,cortex-a7-gic";
69 #interrupt-cells = <3>;
70 interrupt-controller;
80 compatible = "fsl,ifc", "simple-bus";
86 compatible = "fsl,ls1021a-dcfg", "syscon";
88 big-endian;
95 clock-frequency = <0>;
96 voltage-ranges = <1800 1800 3300 3300>;
97 sdhci,auto-cmd12;
98 big-endian;
99 bus-width = <4>;
104 compatible = "fsl,ls1021a-scfg", "syscon";
106 big-endian;
110 #address-cells = <1>;
111 #size-cells = <1>;
115 compatible = "fixed-clock";
116 #clock-cells = <0>;
117 clock-output-names = "sysclk";
121 compatible = "fsl,qoriq-core-pll-2.0";
122 #clock-cells = <1>;
125 clock-output-names = "cga-pll1", "cga-pll1-div2",
126 "cga-pll1-div4";
130 compatible = "fsl,qoriq-core-pll-2.0";
131 #clock-cells = <1>;
134 clock-output-names = "platform-clk", "platform-clk-div2";
138 compatible = "fsl,qoriq-core-mux-2.0";
139 #clock-cells = <0>;
141 clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
143 clock-output-names = "cluster1-clk";
148 compatible = "fsl,vf610-dspi";
149 #address-cells = <1>;
150 #size-cells = <0>;
153 clock-names = "dspi";
155 num-cs = <6>;
156 big-endian;
161 compatible = "fsl,vf610-dspi";
162 #address-cells = <1>;
163 #size-cells = <0>;
166 clock-names = "dspi";
168 num-cs = <6>;
169 big-endian;
174 compatible = "fsl,vf610-qspi";
175 #address-cells = <1>;
176 #size-cells = <0>;
179 reg-names = "QuadSPI", "QuadSPI-memory";
180 num-cs = <2>;
181 big-endian;
185 i2c0: i2c@2180000 {
186 compatible = "fsl,vf610-i2c";
187 #address-cells = <1>;
188 #size-cells = <0>;
191 clock-names = "i2c";
196 i2c1: i2c@2190000 {
197 compatible = "fsl,vf610-i2c";
198 #address-cells = <1>;
199 #size-cells = <0>;
202 clock-names = "i2c";
207 i2c2: i2c@21a0000 {
208 compatible = "fsl,vf610-i2c";
209 #address-cells = <1>;
210 #size-cells = <0>;
213 clock-names = "i2c";
219 compatible = "fsl,16550-FIFO64", "ns16550a";
222 fifo-size = <15>;
227 compatible = "fsl,16550-FIFO64", "ns16550a";
230 fifo-size = <15>;
235 compatible = "fsl,16550-FIFO64", "ns16550a";
238 fifo-size = <15>;
243 compatible = "fsl,16550-FIFO64", "ns16550a";
246 fifo-size = <15>;
251 compatible = "fsl,ls1021a-lpuart";
255 clock-names = "ipg";
260 compatible = "fsl,ls1021a-lpuart";
264 clock-names = "ipg";
269 compatible = "fsl,ls1021a-lpuart";
273 clock-names = "ipg";
278 compatible = "fsl,ls1021a-lpuart";
282 clock-names = "ipg";
287 compatible = "fsl,ls1021a-lpuart";
291 clock-names = "ipg";
296 compatible = "fsl,ls1021a-lpuart";
300 clock-names = "ipg";
305 compatible = "fsl,imx21-wdt";
309 clock-names = "wdog-en";
310 big-endian;
314 compatible = "fsl,vf610-sai";
318 clock-names = "sai";
319 dma-names = "tx", "rx";
322 big-endian;
327 compatible = "fsl,vf610-sai";
331 clock-names = "sai";
332 dma-names = "tx", "rx";
335 big-endian;
340 #dma-cells = <2>;
341 compatible = "fsl,vf610-edma";
347 interrupt-names = "edma-tx", "edma-err";
348 dma-channels = <32>;
349 big-endian;
350 clock-names = "dmamux0", "dmamux1";
358 #address-cells = <1>;
359 #size-cells = <0>;
364 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
372 compatible = "fsl,layerscape-dwc3";
379 compatible = "fsl,ls-pcie", "snps,dw-pcie";
383 reg-names = "dbi", "ctrl", "config";
384 big-endian;
385 #address-cells = <3>;
386 #size-cells = <2>;
388 bus-range = <0x0 0xff>;
390 0x82000000 0x0 0x28000000 0x28000000 0x0 0x08000000>; /* non-prefetchable memory */
394 compatible = "fsl,ls-pcie", "snps,dw-pcie";
398 reg-names = "dbi", "ctrl", "config";
399 big-endian;
400 #address-cells = <3>;
401 #size-cells = <2>;
403 num-lanes = <2>;
404 bus-range = <0x0 0xff>;
406 0x82000000 0x0 0x38000000 0x38000000 0x0 0x08000000>; /* non-prefetchable memory */