Lines Matching +full:0 +full:x34000000
28 #size-cells = <0>;
33 reg = <0xf00>;
40 reg = <0xf01>;
71 reg = <0x1401000 0x1000>,
72 <0x1402000 0x1000>,
73 <0x1404000 0x2000>,
74 <0x1406000 0x2000>;
81 reg = <0x1530000 0x10000>;
87 reg = <0x1ee0000 0x10000>;
93 reg = <0x1560000 0x10000>;
95 clock-frequency = <0>;
105 reg = <0x1570000 0x10000>;
112 ranges = <0x0 0x1ee1000 0x10000>;
116 #clock-cells = <0>;
123 reg = <0x800 0x10>;
132 reg = <0xc00 0x10>;
137 cluster1_clk: clk0c0@0 {
139 #clock-cells = <0>;
140 reg = <0x0 0x10>;
142 clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
150 #size-cells = <0>;
151 reg = <0x2100000 0x10000>;
163 #size-cells = <0>;
164 reg = <0x2110000 0x10000>;
176 #size-cells = <0>;
177 reg = <0x1550000 0x10000>,
178 <0x40000000 0x4000000>;
188 #size-cells = <0>;
189 reg = <0x2180000 0x10000>;
199 #size-cells = <0>;
200 reg = <0x2190000 0x10000>;
210 #size-cells = <0>;
211 reg = <0x21a0000 0x10000>;
220 reg = <0x21c0500 0x100>;
228 reg = <0x21c0600 0x100>;
236 reg = <0x21d0500 0x100>;
244 reg = <0x21d0600 0x100>;
252 reg = <0x2950000 0x1000>;
261 reg = <0x2960000 0x1000>;
270 reg = <0x2970000 0x1000>;
279 reg = <0x2980000 0x1000>;
288 reg = <0x2990000 0x1000>;
297 reg = <0x29a0000 0x1000>;
306 reg = <0x2ad0000 0x10000>;
315 reg = <0x2b50000 0x10000>;
328 reg = <0x2b60000 0x10000>;
342 reg = <0x2c00000 0x10000>,
343 <0x2c10000 0x10000>,
344 <0x2c20000 0x10000>;
359 #size-cells = <0>;
360 reg = <0x2d24000 0x4000>;
365 reg = <0x8600000 0x1000>;
373 reg = <0x3100000 0x10000>;
380 reg = <0x03400000 0x20000 /* dbi registers */
381 0x01570000 0x10000 /* pf controls registers */
382 0x24000000 0x20000>; /* configuration space */
388 bus-range = <0x0 0xff>;
389 ranges = <0x81000000 0x0 0x00000000 0x24020000 0x0 0x00010000 /* downstream I/O */
390 0x82000000 0x0 0x28000000 0x28000000 0x0 0x08000000>; /* non-prefetchable memory */
395 reg = <0x03500000 0x10000 /* dbi registers */
396 0x01570000 0x10000 /* pf controls registers */
397 0x34000000 0x20000>; /* configuration space */
404 bus-range = <0x0 0xff>;
405 ranges = <0x81000000 0x0 0x00000000 0x34020000 0x0 0x00010000 /* downstream I/O */
406 0x82000000 0x0 0x38000000 0x38000000 0x0 0x08000000>; /* non-prefetchable memory */