arm/dts/ls1021a-qds.dtsi

4  * Copyright 2013-2015 Freescale Semiconductor, Inc.
6  * SPDX-License-Identifier:	GPL-2.0+
26 	bus-num = <0>;
30 		#address-cells = <1>;
31 		#size-cells = <1>;
33 		spi-max-frequency = <16000000>;
34 		spi-cpol;
35 		spi-cpha;
41 	bus-num = <0>;
45 		#address-cells = <1>;
46 		#size-cells = <1>;
47 		compatible = "spi-flash";
48 		spi-max-frequency = <20000000>;
56 	pca9547: mux@77 {
58 		#address-cells = <1>;
59 		#size-cells = <0>;
62 			#address-cells = <1>;
63 			#size-cells = <0>;
74 			#address-cells = <1>;
75 			#size-cells = <0>;
81 				shunt-resistor = <1000>;
87 				shunt-resistor = <1000>;
92 			#address-cells = <1>;
93 			#size-cells = <0>;
115 	#address-cells = <2>;
116 	#size-cells = <1>;
124 		#address-cells = <1>;
125 		#size-cells = <1>;
126 		compatible = "cfi-flash";
128 		bank-width = <2>;
129 		device-width = <1>;
132 	fpga: board-control@3,0 {
133 		#address-cells = <1>;
134 		#size-cells = <1>;
135 		compatible = "simple-bus";
137 		bank-width = <1>;
138 		device-width = <1>;
141 		mdio-mux-emi1 {
142 			compatible = "mdio-mux-mmioreg";
143 			mdio-parent-bus = <&mdio0>;
144 			#address-cells = <1>;
145 			#size-cells = <0>;
147 			mux-mask = <0xe0>; /* EMI1[2:0] */
150 			ls1021amdio0: mdio@0 {
152 				#address-cells = <1>;
153 				#size-cells = <0>;
154 				rgmii_phy1: ethernet-phy@1 {
159 			ls1021amdio1: mdio@20 {
161 				#address-cells = <1>;
162 				#size-cells = <0>;
163 				rgmii_phy2: ethernet-phy@2 {
168 			ls1021amdio2: mdio@40 {
170 				#address-cells = <1>;
171 				#size-cells = <0>;
172 				rgmii_phy3: ethernet-phy@3 {
177 			ls1021amdio3: mdio@60 {
179 				#address-cells = <1>;
180 				#size-cells = <0>;
181 				sgmii_phy1c: ethernet-phy@1c {
186 			ls1021amdio4: mdio@80 {
188 				#address-cells = <1>;
189 				#size-cells = <0>;
190 				sgmii_phy1d: ethernet-phy@1d {
203 	tbi0: tbi-phy@8 {
205 		device_type = "tbi-phy";