Lines Matching +full:0 +full:x021b0000
51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0>;
88 reg = <0x00a01000 0x1000>,
89 <0x00a02000 0x100>;
94 #size-cells = <0>;
96 ckil: clock@0 {
98 reg = <0>;
99 #clock-cells = <0>;
107 #clock-cells = <0>;
115 #clock-cells = <0>;
116 clock-frequency = <0>;
123 #clock-cells = <0>;
124 clock-frequency = <0>;
164 reg = <0x00900000 0x4000>;
169 reg = <0x00904000 0x1000>;
174 reg = <0x00905000 0x1B000>;
179 reg = <0x01804000 0x2000>;
194 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
205 dmas = <&dma_apbh 0>;
214 reg = <0x02000000 0x100000>;
221 reg = <0x02000000 0x40000>;
226 reg = <0x02004000 0x4000>;
228 dmas = <&sdma 41 18 0>,
229 <&sdma 42 18 0>;
248 #size-cells = <0>;
250 reg = <0x02008000 0x4000>;
262 #size-cells = <0>;
264 reg = <0x0200c000 0x4000>;
276 #size-cells = <0>;
278 reg = <0x02010000 0x4000>;
290 #size-cells = <0>;
292 reg = <0x02014000 0x4000>;
305 reg = <0x02018000 0x4000>;
310 dmas = <&sdma 43 4 0>, <&sdma 44 4 0>;
318 reg = <0x02020000 0x4000>;
328 reg = <0x02024000 0x4000>;
337 dmas = <&sdma 0 21 0>, <&sdma 47 21 0>;
339 dma-source = <&gpr 0 14 0 15>;
346 reg = <0x02028000 0x4000>;
351 <&clks 0>, <&clks 0>;
354 dmas = <&sdma 35 24 0>, <&sdma 36 24 0>;
361 reg = <0x0202c000 0x4000>;
366 <&clks 0>, <&clks 0>;
369 dmas = <&sdma 37 24 0>, <&sdma 38 24 0>;
376 reg = <0x02030000 0x4000>;
381 <&clks 0>, <&clks 0>;
384 dmas = <&sdma 39 24 0>, <&sdma 40 24 0>;
390 reg = <0x02034000 0x4000>;
393 <&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>,
394 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
395 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
396 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
397 <&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>,
416 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
427 reg = <0x02080000 0x4000>;
437 reg = <0x02084000 0x4000>;
447 reg = <0x02088000 0x4000>;
457 reg = <0x0208c000 0x4000>;
467 reg = <0x02090000 0x4000>;
472 stop-mode = <&gpr 0x10 1 0x10 17>;
478 reg = <0x02094000 0x4000>;
483 stop-mode = <&gpr 0x10 2 0x10 18>;
489 reg = <0x02098000 0x4000>;
498 reg = <0x0209c000 0x4000>;
509 reg = <0x020a0000 0x4000>;
520 reg = <0x020a4000 0x4000>;
531 reg = <0x020a8000 0x4000>;
542 reg = <0x020ac000 0x4000>;
553 reg = <0x020b0000 0x4000>;
559 reg = <0x020b4000 0x4000>;
569 stop-mode = <&gpr 0x10 4>;
573 fsl,wakeup_irq = <0>;
579 reg = <0x020b8000 0x4000>;
587 reg = <0x020bc000 0x4000>;
594 reg = <0x020c0000 0x4000>;
602 reg = <0x020c4000 0x4000>;
613 reg = <0x020c8000 0x1000>;
623 anatop-reg-offset = <0x120>;
626 anatop-min-bit-val = <0>;
629 anatop-enable-bit = <0>;
638 anatop-reg-offset = <0x140>;
639 anatop-vol-bit-shift = <0>;
641 anatop-delay-reg-offset = <0x170>;
655 anatop-reg-offset = <0x140>;
658 anatop-delay-reg-offset = <0x170>;
669 reg = <0x020c9000 0x1000>;
678 reg = <0x020ca000 0x1000>;
694 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
695 reg = <0x020cc000 0x4000>;
698 compatible = "fsl,sec-v4.0-mon-rtc-lp";
700 offset = <0x34>;
707 offset = <0x38>;
708 mask = <0x61>;
712 compatible = "fsl,sec-v4.0-pwrkey";
721 reg = <0x020d0000 0x4000>;
726 reg = <0x020d4000 0x4000>;
732 reg = <0x020d8000 0x4000>;
740 reg = <0x020dc000 0x4000>;
745 fsl,mf-mix-wakeup-irq = <0xfc00000 0x7d00 0x0 0x1400640>;
750 reg = <0x020e0000 0x4000>;
755 reg = <0x020e4000 0x4000>;
766 reg = <0x020e8000 0x4000>;
775 reg = <0x020ec000 0x4000>;
787 reg = <0x020f0000 0x4000>;
797 reg = <0x020f4000 0x4000>;
807 reg = <0x020f8000 0x4000>;
817 reg = <0x020fc000 0x4000>;
830 reg = <0x02100000 0x100000>;
835 reg = <0x02184000 0x200>;
839 fsl,usbmisc = <&usbmisc 0>;
841 ahb-burst-config = <0x0>;
842 tx-burst-size-dword = <0x10>;
843 rx-burst-size-dword = <0x10>;
849 reg = <0x02184200 0x200>;
854 ahb-burst-config = <0x0>;
855 tx-burst-size-dword = <0x10>;
856 rx-burst-size-dword = <0x10>;
863 reg = <0x02184800 0x200>;
868 reg = <0x02188000 0x4000>;
878 stop-mode = <&gpr 0x10 3>;
882 fsl,wakeup_irq = <0>;
888 reg = <0x02190000 0x4000>;
901 reg = <0x02194000 0x4000>;
914 reg = <0x02198000 0x4000>;
924 #size-cells = <0>;
926 reg = <0x021a0000 0x4000>;
934 #size-cells = <0>;
936 reg = <0x021a4000 0x4000>;
944 #size-cells = <0>;
946 reg = <0x021a8000 0x4000>;
954 reg = <0x021ac000 0x4000>;
959 reg = <0x021b0000 0x4000>;
964 reg = <0x021b8000 0x4000>;
971 reg = <0x021bc000 0x4000>;
977 reg = <0x021c0000 0x4000>;
984 reg = <0x021c4000 0x4000>;
995 reg = <0x021c8000 0x4000>;
1006 reg = <0x021cc000 0x4000>;
1016 #size-cells = <0>;
1018 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1030 reg = <0x021e8000 0x4000>;
1035 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1043 reg = <0x021ec000 0x4000>;
1048 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1056 reg = <0x021f0000 0x4000>;
1061 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1069 reg = <0x021f4000 0x4000>;
1074 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1081 #size-cells = <0>;
1083 reg = <0x021f8000 0x4000>;
1092 reg = <0x021fc000 0x4000>;
1097 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1107 reg = <0x02200000 0x100000>;
1111 reg = <0x02280000 0x4000>;
1121 reg = <0x02284000 0x4000>;
1128 reg = <0x02288000 0x4000>;
1133 dmas = <&sdma 45 4 0>, <&sdma 46 4 0>;
1141 reg = <0x0228c000 0x4000>;
1146 /* epdc-ram = <&gpr 0x4 30>; */
1152 reg = <0x02290000 0x10000>;
1155 snvs_gpr: snvs-gpr@0x02294000 {
1157 reg = <0x02294000 0x10000>;