Lines Matching +full:anatop +full:- +full:reg +full:- +full:offset
9 #include <dt-bindings/clock/imx6ul-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "imx6ul-pinfunc.h"
53 #address-cells = <1>;
54 #size-cells = <0>;
57 compatible = "arm,cortex-a7";
59 reg = <0>;
60 clock-latency = <61036>; /* two CLK32 periods */
61 operating-points = <
67 fsl,soc-operating-points = <
84 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
88 arm-supply = <®_arm>;
89 soc-supply = <®_soc>;
93 intc: interrupt-controller@00a01000 {
94 compatible = "arm,cortex-a7-gic";
95 #interrupt-cells = <3>;
96 interrupt-controller;
97 reg = <0x00a01000 0x1000>,
103 ckil: clock-cli {
104 compatible = "fixed-clock";
105 #clock-cells = <0>;
106 clock-frequency = <32768>;
107 clock-output-names = "ckil";
110 osc: clock-osc {
111 compatible = "fixed-clock";
112 #clock-cells = <0>;
113 clock-frequency = <24000000>;
114 clock-output-names = "osc";
117 ipp_di0: clock-di0 {
118 compatible = "fixed-clock";
119 #clock-cells = <0>;
120 clock-frequency = <0>;
121 clock-output-names = "ipp_di0";
124 ipp_di1: clock-di1 {
125 compatible = "fixed-clock";
126 #clock-cells = <0>;
127 clock-frequency = <0>;
128 clock-output-names = "ipp_di1";
132 #address-cells = <1>;
133 #size-cells = <1>;
134 compatible = "simple-bus";
135 interrupt-parent = <&gpc>;
139 compatible = "arm,cortex-a7-pmu";
145 compatible = "mmio-sram";
146 reg = <0x00900000 0x20000>;
149 dma_apbh: dma-apbh@01804000 {
150 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
151 reg = <0x01804000 0x2000>;
156 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
157 #dma-cells = <1>;
158 dma-channels = <4>;
162 gpmi: gpmi-nand@01806000 {
163 compatible = "fsl,imx6q-gpmi-nand";
164 #address-cells = <1>;
165 #size-cells = <1>;
166 reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
167 reg-names = "gpmi-nand", "bch";
169 interrupt-names = "bch";
175 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
178 dma-names = "rx-tx";
182 aips1: aips-bus@02000000 {
183 compatible = "fsl,aips-bus", "simple-bus";
184 #address-cells = <1>;
185 #size-cells = <1>;
186 reg = <0x02000000 0x100000>;
189 spba-bus@02000000 {
190 compatible = "fsl,spba-bus", "simple-bus";
191 #address-cells = <1>;
192 #size-cells = <1>;
193 reg = <0x02000000 0x40000>;
197 #address-cells = <1>;
198 #size-cells = <0>;
199 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
200 reg = <0x02008000 0x4000>;
204 clock-names = "ipg", "per";
209 #address-cells = <1>;
210 #size-cells = <0>;
211 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
212 reg = <0x0200c000 0x4000>;
216 clock-names = "ipg", "per";
221 #address-cells = <1>;
222 #size-cells = <0>;
223 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
224 reg = <0x02010000 0x4000>;
228 clock-names = "ipg", "per";
233 #address-cells = <1>;
234 #size-cells = <0>;
235 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
236 reg = <0x02014000 0x4000>;
240 clock-names = "ipg", "per";
245 compatible = "fsl,imx6ul-uart",
246 "fsl,imx6q-uart";
247 reg = <0x02018000 0x4000>;
251 clock-names = "ipg", "per";
256 compatible = "fsl,imx6ul-uart",
257 "fsl,imx6q-uart";
258 reg = <0x02020000 0x4000>;
262 clock-names = "ipg", "per";
267 compatible = "fsl,imx6ul-uart",
268 "fsl,imx6q-uart";
269 reg = <0x02024000 0x4000>;
273 clock-names = "ipg", "per";
278 #sound-dai-cells = <0>;
279 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
280 reg = <0x02028000 0x4000>;
285 clock-names = "bus", "mclk1", "mclk2", "mclk3";
288 dma-names = "rx", "tx";
293 #sound-dai-cells = <0>;
294 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
295 reg = <0x0202c000 0x4000>;
300 clock-names = "bus", "mclk1", "mclk2", "mclk3";
303 dma-names = "rx", "tx";
308 #sound-dai-cells = <0>;
309 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
310 reg = <0x02030000 0x4000>;
315 clock-names = "bus", "mclk1", "mclk2", "mclk3";
318 dma-names = "rx", "tx";
324 compatible = "fsl,imx6ul-tsc";
325 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
330 clock-names = "tsc", "adc";
335 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
336 reg = <0x02080000 0x4000>;
340 clock-names = "ipg", "per";
341 #pwm-cells = <2>;
346 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
347 reg = <0x02084000 0x4000>;
351 clock-names = "ipg", "per";
352 #pwm-cells = <2>;
357 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
358 reg = <0x02088000 0x4000>;
362 clock-names = "ipg", "per";
363 #pwm-cells = <2>;
368 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
369 reg = <0x0208c000 0x4000>;
373 clock-names = "ipg", "per";
374 #pwm-cells = <2>;
379 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
380 reg = <0x02090000 0x4000>;
384 clock-names = "ipg", "per";
389 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
390 reg = <0x02094000 0x4000>;
394 clock-names = "ipg", "per";
399 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
400 reg = <0x02098000 0x4000>;
404 clock-names = "ipg", "per";
408 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
409 reg = <0x0209c000 0x4000>;
412 gpio-controller;
413 #gpio-cells = <2>;
414 interrupt-controller;
415 #interrupt-cells = <2>;
416 gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>,
421 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
422 reg = <0x020a0000 0x4000>;
425 gpio-controller;
426 #gpio-cells = <2>;
427 interrupt-controller;
428 #interrupt-cells = <2>;
429 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
433 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
434 reg = <0x020a4000 0x4000>;
437 gpio-controller;
438 #gpio-cells = <2>;
439 interrupt-controller;
440 #interrupt-cells = <2>;
441 gpio-ranges = <&iomuxc 0 65 29>;
445 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
446 reg = <0x020a8000 0x4000>;
449 gpio-controller;
450 #gpio-cells = <2>;
451 interrupt-controller;
452 #interrupt-cells = <2>;
453 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
457 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
458 reg = <0x020ac000 0x4000>;
461 gpio-controller;
462 #gpio-cells = <2>;
463 interrupt-controller;
464 #interrupt-cells = <2>;
465 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
469 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
470 reg = <0x020b4000 0x4000>;
478 clock-names = "ipg", "ahb", "ptp",
480 fsl,num-tx-queues=<1>;
481 fsl,num-rx-queues=<1>;
486 compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
487 reg = <0x020b8000 0x4000>;
494 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
495 reg = <0x020bc000 0x4000>;
501 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
502 reg = <0x020c0000 0x4000>;
509 compatible = "fsl,imx6ul-ccm";
510 reg = <0x020c4000 0x4000>;
513 #clock-cells = <1>;
515 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
518 anatop: anatop@020c8000 { label
519 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
520 "syscon", "simple-bus";
521 reg = <0x020c8000 0x1000>;
526 reg_3p0: regulator-3p0 {
527 compatible = "fsl,anatop-regulator";
528 regulator-name = "vdd3p0";
529 regulator-min-microvolt = <2625000>;
530 regulator-max-microvolt = <3400000>;
531 anatop-reg-offset = <0x120>;
532 anatop-vol-bit-shift = <8>;
533 anatop-vol-bit-width = <5>;
534 anatop-min-bit-val = <0>;
535 anatop-min-voltage = <2625000>;
536 anatop-max-voltage = <3400000>;
537 anatop-enable-bit = <0>;
540 reg_arm: regulator-vddcore {
541 compatible = "fsl,anatop-regulator";
542 regulator-name = "cpu";
543 regulator-min-microvolt = <725000>;
544 regulator-max-microvolt = <1450000>;
545 regulator-always-on;
546 anatop-reg-offset = <0x140>;
547 anatop-vol-bit-shift = <0>;
548 anatop-vol-bit-width = <5>;
549 anatop-delay-reg-offset = <0x170>;
550 anatop-delay-bit-shift = <24>;
551 anatop-delay-bit-width = <2>;
552 anatop-min-bit-val = <1>;
553 anatop-min-voltage = <725000>;
554 anatop-max-voltage = <1450000>;
557 reg_soc: regulator-vddsoc {
558 compatible = "fsl,anatop-regulator";
559 regulator-name = "vddsoc";
560 regulator-min-microvolt = <725000>;
561 regulator-max-microvolt = <1450000>;
562 regulator-always-on;
563 anatop-reg-offset = <0x140>;
564 anatop-vol-bit-shift = <18>;
565 anatop-vol-bit-width = <5>;
566 anatop-delay-reg-offset = <0x170>;
567 anatop-delay-bit-shift = <28>;
568 anatop-delay-bit-width = <2>;
569 anatop-min-bit-val = <1>;
570 anatop-min-voltage = <725000>;
571 anatop-max-voltage = <1450000>;
576 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
577 reg = <0x020c9000 0x1000>;
580 phy-3p0-supply = <®_3p0>;
581 fsl,anatop = <&anatop>;
585 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
586 reg = <0x020ca000 0x1000>;
589 phy-3p0-supply = <®_3p0>;
590 fsl,anatop = <&anatop>;
594 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
595 reg = <0x020cc000 0x4000>;
597 snvs_rtc: snvs-rtc-lp {
598 compatible = "fsl,sec-v4.0-mon-rtc-lp";
600 offset = <0x34>;
605 snvs_poweroff: snvs-poweroff {
606 compatible = "syscon-poweroff";
608 offset = <0x38>;
613 snvs_pwrkey: snvs-powerkey {
614 compatible = "fsl,sec-v4.0-pwrkey";
618 wakeup-source;
623 reg = <0x020d0000 0x4000>;
628 reg = <0x020d4000 0x4000>;
633 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
634 reg = <0x020d8000 0x4000>;
637 #reset-cells = <1>;
641 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
642 reg = <0x020dc000 0x4000>;
643 interrupt-controller;
644 #interrupt-cells = <3>;
646 interrupt-parent = <&intc>;
650 compatible = "fsl,imx6ul-iomuxc";
651 reg = <0x020e0000 0x4000>;
654 gpr: iomuxc-gpr@020e4000 {
655 compatible = "fsl,imx6ul-iomuxc-gpr",
656 "fsl,imx6q-iomuxc-gpr", "syscon";
657 reg = <0x020e4000 0x4000>;
661 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
662 reg = <0x020e8000 0x4000>;
666 clock-names = "ipg", "per";
670 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
671 "fsl,imx35-sdma";
672 reg = <0x020ec000 0x4000>;
676 clock-names = "ipg", "ahb";
677 #dma-cells = <3>;
678 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
682 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
683 reg = <0x020f0000 0x4000>;
687 clock-names = "ipg", "per";
688 #pwm-cells = <2>;
693 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
694 reg = <0x020f4000 0x4000>;
698 clock-names = "ipg", "per";
699 #pwm-cells = <2>;
704 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
705 reg = <0x020f8000 0x4000>;
709 clock-names = "ipg", "per";
710 #pwm-cells = <2>;
715 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
716 reg = <0x020fc000 0x4000>;
720 clock-names = "ipg", "per";
721 #pwm-cells = <2>;
726 aips2: aips-bus@02100000 {
727 compatible = "fsl,aips-bus", "simple-bus";
728 #address-cells = <1>;
729 #size-cells = <1>;
730 reg = <0x02100000 0x100000>;
734 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
735 reg = <0x02184000 0x200>;
740 fsl,anatop = <&anatop>;
741 ahb-burst-config = <0x0>;
742 tx-burst-size-dword = <0x10>;
743 rx-burst-size-dword = <0x10>;
748 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
749 reg = <0x02184200 0x200>;
754 ahb-burst-config = <0x0>;
755 tx-burst-size-dword = <0x10>;
756 rx-burst-size-dword = <0x10>;
761 #index-cells = <1>;
762 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
763 reg = <0x02184800 0x200>;
767 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
768 reg = <0x02188000 0x4000>;
776 clock-names = "ipg", "ahb", "ptp",
778 fsl,num-tx-queues=<1>;
779 fsl,num-rx-queues=<1>;
784 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
785 reg = <0x02190000 0x4000>;
790 clock-names = "ipg", "ahb", "per";
791 bus-width = <4>;
796 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
797 reg = <0x02194000 0x4000>;
802 clock-names = "ipg", "ahb", "per";
803 bus-width = <4>;
808 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
809 reg = <0x02198000 0x4000>;
812 num-channels = <2>;
813 clock-names = "adc";
814 fsl,adck-max-frequency = <30000000>, <40000000>,
820 #address-cells = <1>;
821 #size-cells = <0>;
822 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
823 reg = <0x021a0000 0x4000>;
830 #address-cells = <1>;
831 #size-cells = <0>;
832 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
833 reg = <0x021a4000 0x4000>;
840 #address-cells = <1>;
841 #size-cells = <0>;
842 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
843 reg = <0x021a8000 0x4000>;
850 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
851 reg = <0x021b0000 0x4000>;
855 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
856 reg = <0x021c8000 0x4000>;
861 clock-names = "pix", "axi", "disp_axi";
866 #address-cells = <1>;
867 #size-cells = <0>;
868 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
869 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
870 reg-names = "QuadSPI", "QuadSPI-memory";
874 clock-names = "qspi_en", "qspi";
879 compatible = "fsl,imx6ul-uart",
880 "fsl,imx6q-uart";
881 reg = <0x021e8000 0x4000>;
885 clock-names = "ipg", "per";
890 compatible = "fsl,imx6ul-uart",
891 "fsl,imx6q-uart";
892 reg = <0x021ec000 0x4000>;
896 clock-names = "ipg", "per";
901 compatible = "fsl,imx6ul-uart",
902 "fsl,imx6q-uart";
903 reg = <0x021f0000 0x4000>;
907 clock-names = "ipg", "per";
912 compatible = "fsl,imx6ul-uart",
913 "fsl,imx6q-uart";
914 reg = <0x021f4000 0x4000>;
918 clock-names = "ipg", "per";
923 #address-cells = <1>;
924 #size-cells = <0>;
925 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
926 reg = <0x021f8000 0x4000>;
933 compatible = "fsl,imx6ul-uart",
934 "fsl,imx6q-uart";
935 reg = <0x021fc000 0x4000>;
939 clock-names = "ipg", "per";