Lines Matching +full:anatop +full:- +full:reg +full:- +full:offset
9 #include <dt-bindings/clock/imx6sx-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "imx6sx-pinfunc.h"
53 #address-cells = <1>;
54 #size-cells = <0>;
57 compatible = "arm,cortex-a9";
59 reg = <0>;
60 next-level-cache = <&L2>;
61 operating-points = <
68 fsl,soc-operating-points = <
75 clock-latency = <61036>; /* two CLK32 periods */
81 clock-names = "arm", "pll2_pfd2_396m", "step",
83 arm-supply = <®_arm>;
84 soc-supply = <®_soc>;
88 intc: interrupt-controller@00a01000 {
89 compatible = "arm,cortex-a9-gic";
90 #interrupt-cells = <3>;
91 interrupt-controller;
92 reg = <0x00a01000 0x1000>,
94 interrupt-parent = <&intc>;
98 #address-cells = <1>;
99 #size-cells = <0>;
102 compatible = "fixed-clock";
103 reg = <0>;
104 #clock-cells = <0>;
105 clock-frequency = <32768>;
106 clock-output-names = "ckil";
110 compatible = "fixed-clock";
111 reg = <1>;
112 #clock-cells = <0>;
113 clock-frequency = <24000000>;
114 clock-output-names = "osc";
118 compatible = "fixed-clock";
119 reg = <2>;
120 #clock-cells = <0>;
121 clock-frequency = <0>;
122 clock-output-names = "ipp_di0";
126 compatible = "fixed-clock";
127 reg = <3>;
128 #clock-cells = <0>;
129 clock-frequency = <0>;
130 clock-output-names = "ipp_di1";
135 #address-cells = <1>;
136 #size-cells = <1>;
137 compatible = "simple-bus";
138 interrupt-parent = <&gpc>;
142 compatible = "arm,cortex-a9-pmu";
147 compatible = "mmio-sram";
148 reg = <0x00900000 0x20000>;
152 L2: l2-cache@00a02000 {
153 compatible = "arm,pl310-cache";
154 reg = <0x00a02000 0x1000>;
156 cache-unified;
157 cache-level = <2>;
158 arm,tag-latency = <4 2 3>;
159 arm,data-latency = <4 2 3>;
164 reg = <0x01800000 0x4000>;
169 clock-names = "bus", "core", "shader";
172 dma_apbh: dma-apbh@01804000 {
173 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
174 reg = <0x01804000 0x2000>;
179 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
180 #dma-cells = <1>;
181 dma-channels = <4>;
185 gpmi: gpmi-nand@01806000{
186 compatible = "fsl,imx6sx-gpmi-nand";
187 #address-cells = <1>;
188 #size-cells = <1>;
189 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
190 reg-names = "gpmi-nand", "bch";
192 interrupt-names = "bch";
198 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
201 dma-names = "rx-tx";
205 aips1: aips-bus@02000000 {
206 compatible = "fsl,aips-bus", "simple-bus";
207 #address-cells = <1>;
208 #size-cells = <1>;
209 reg = <0x02000000 0x100000>;
212 spba-bus@02000000 {
213 compatible = "fsl,spba-bus", "simple-bus";
214 #address-cells = <1>;
215 #size-cells = <1>;
216 reg = <0x02000000 0x40000>;
220 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
221 reg = <0x02004000 0x4000>;
225 dma-names = "rx", "tx";
233 clock-names = "core", "rxtx0",
242 #address-cells = <1>;
243 #size-cells = <0>;
244 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
245 reg = <0x02008000 0x4000>;
249 clock-names = "ipg", "per";
254 #address-cells = <1>;
255 #size-cells = <0>;
256 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
257 reg = <0x0200c000 0x4000>;
261 clock-names = "ipg", "per";
266 #address-cells = <1>;
267 #size-cells = <0>;
268 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
269 reg = <0x02010000 0x4000>;
273 clock-names = "ipg", "per";
278 #address-cells = <1>;
279 #size-cells = <0>;
280 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
281 reg = <0x02014000 0x4000>;
285 clock-names = "ipg", "per";
290 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
291 reg = <0x02020000 0x4000>;
295 clock-names = "ipg", "per";
297 dma-names = "rx", "tx";
302 reg = <0x02024000 0x4000>;
309 clock-names = "core", "mem", "extal",
315 #sound-dai-cells = <0>;
316 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
317 reg = <0x02028000 0x4000>;
321 clock-names = "ipg", "baud";
323 dma-names = "rx", "tx";
324 fsl,fifo-depth = <15>;
329 #sound-dai-cells = <0>;
330 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
331 reg = <0x0202c000 0x4000>;
335 clock-names = "ipg", "baud";
337 dma-names = "rx", "tx";
338 fsl,fifo-depth = <15>;
343 #sound-dai-cells = <0>;
344 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
345 reg = <0x02030000 0x4000>;
349 clock-names = "ipg", "baud";
351 dma-names = "rx", "tx";
352 fsl,fifo-depth = <15>;
357 reg = <0x02034000 0x4000>;
363 clock-names = "mem", "ipg", "asrck", "spba";
367 dma-names = "rxa", "rxb", "rxc",
374 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
375 reg = <0x02080000 0x4000>;
379 clock-names = "ipg", "per";
380 #pwm-cells = <2>;
384 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
385 reg = <0x02084000 0x4000>;
389 clock-names = "ipg", "per";
390 #pwm-cells = <2>;
394 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
395 reg = <0x02088000 0x4000>;
399 clock-names = "ipg", "per";
400 #pwm-cells = <2>;
404 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
405 reg = <0x0208c000 0x4000>;
409 clock-names = "ipg", "per";
410 #pwm-cells = <2>;
414 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
415 reg = <0x02090000 0x4000>;
419 clock-names = "ipg", "per";
424 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
425 reg = <0x02094000 0x4000>;
429 clock-names = "ipg", "per";
434 compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt";
435 reg = <0x02098000 0x4000>;
439 clock-names = "ipg", "per";
443 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
444 reg = <0x0209c000 0x4000>;
447 gpio-controller;
448 #gpio-cells = <2>;
449 interrupt-controller;
450 #interrupt-cells = <2>;
451 gpio-ranges = <&iomuxc 0 5 26>;
455 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
456 reg = <0x020a0000 0x4000>;
459 gpio-controller;
460 #gpio-cells = <2>;
461 interrupt-controller;
462 #interrupt-cells = <2>;
463 gpio-ranges = <&iomuxc 0 31 20>;
467 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
468 reg = <0x020a4000 0x4000>;
471 gpio-controller;
472 #gpio-cells = <2>;
473 interrupt-controller;
474 #interrupt-cells = <2>;
475 gpio-ranges = <&iomuxc 0 51 29>;
479 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
480 reg = <0x020a8000 0x4000>;
483 gpio-controller;
484 #gpio-cells = <2>;
485 interrupt-controller;
486 #interrupt-cells = <2>;
487 gpio-ranges = <&iomuxc 0 80 32>;
491 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
492 reg = <0x020ac000 0x4000>;
495 gpio-controller;
496 #gpio-cells = <2>;
497 interrupt-controller;
498 #interrupt-cells = <2>;
499 gpio-ranges = <&iomuxc 0 112 24>;
503 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
504 reg = <0x020b0000 0x4000>;
507 gpio-controller;
508 #gpio-cells = <2>;
509 interrupt-controller;
510 #interrupt-cells = <2>;
511 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
515 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
516 reg = <0x020b4000 0x4000>;
519 gpio-controller;
520 #gpio-cells = <2>;
521 interrupt-controller;
522 #interrupt-cells = <2>;
523 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
527 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
528 reg = <0x020b8000 0x4000>;
535 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
536 reg = <0x020bc000 0x4000>;
542 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
543 reg = <0x020c0000 0x4000>;
550 compatible = "fsl,imx6sx-ccm";
551 reg = <0x020c4000 0x4000>;
554 #clock-cells = <1>;
556 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
559 anatop: anatop@020c8000 { label
560 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
561 "syscon", "simple-bus";
562 reg = <0x020c8000 0x1000>;
567 regulator-1p1 {
568 compatible = "fsl,anatop-regulator";
569 regulator-name = "vdd1p1";
570 regulator-min-microvolt = <800000>;
571 regulator-max-microvolt = <1375000>;
572 regulator-always-on;
573 anatop-reg-offset = <0x110>;
574 anatop-vol-bit-shift = <8>;
575 anatop-vol-bit-width = <5>;
576 anatop-min-bit-val = <4>;
577 anatop-min-voltage = <800000>;
578 anatop-max-voltage = <1375000>;
581 regulator-3p0 {
582 compatible = "fsl,anatop-regulator";
583 regulator-name = "vdd3p0";
584 regulator-min-microvolt = <2800000>;
585 regulator-max-microvolt = <3150000>;
586 regulator-always-on;
587 anatop-reg-offset = <0x120>;
588 anatop-vol-bit-shift = <8>;
589 anatop-vol-bit-width = <5>;
590 anatop-min-bit-val = <0>;
591 anatop-min-voltage = <2625000>;
592 anatop-max-voltage = <3400000>;
595 regulator-2p5 {
596 compatible = "fsl,anatop-regulator";
597 regulator-name = "vdd2p5";
598 regulator-min-microvolt = <2100000>;
599 regulator-max-microvolt = <2875000>;
600 regulator-always-on;
601 anatop-reg-offset = <0x130>;
602 anatop-vol-bit-shift = <8>;
603 anatop-vol-bit-width = <5>;
604 anatop-min-bit-val = <0>;
605 anatop-min-voltage = <2100000>;
606 anatop-max-voltage = <2875000>;
609 reg_arm: regulator-vddcore {
610 compatible = "fsl,anatop-regulator";
611 regulator-name = "vddarm";
612 regulator-min-microvolt = <725000>;
613 regulator-max-microvolt = <1450000>;
614 regulator-always-on;
615 anatop-reg-offset = <0x140>;
616 anatop-vol-bit-shift = <0>;
617 anatop-vol-bit-width = <5>;
618 anatop-delay-reg-offset = <0x170>;
619 anatop-delay-bit-shift = <24>;
620 anatop-delay-bit-width = <2>;
621 anatop-min-bit-val = <1>;
622 anatop-min-voltage = <725000>;
623 anatop-max-voltage = <1450000>;
626 reg_pcie: regulator-vddpcie {
627 compatible = "fsl,anatop-regulator";
628 regulator-name = "vddpcie";
629 regulator-min-microvolt = <725000>;
630 regulator-max-microvolt = <1450000>;
631 anatop-reg-offset = <0x140>;
632 anatop-vol-bit-shift = <9>;
633 anatop-vol-bit-width = <5>;
634 anatop-delay-reg-offset = <0x170>;
635 anatop-delay-bit-shift = <26>;
636 anatop-delay-bit-width = <2>;
637 anatop-min-bit-val = <1>;
638 anatop-min-voltage = <725000>;
639 anatop-max-voltage = <1450000>;
642 reg_soc: regulator-vddsoc {
643 compatible = "fsl,anatop-regulator";
644 regulator-name = "vddsoc";
645 regulator-min-microvolt = <725000>;
646 regulator-max-microvolt = <1450000>;
647 regulator-always-on;
648 anatop-reg-offset = <0x140>;
649 anatop-vol-bit-shift = <18>;
650 anatop-vol-bit-width = <5>;
651 anatop-delay-reg-offset = <0x170>;
652 anatop-delay-bit-shift = <28>;
653 anatop-delay-bit-width = <2>;
654 anatop-min-bit-val = <1>;
655 anatop-min-voltage = <725000>;
656 anatop-max-voltage = <1450000>;
661 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
663 fsl,tempmon = <&anatop>;
664 fsl,tempmon-data = <&ocotp>;
669 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
670 reg = <0x020c9000 0x1000>;
673 fsl,anatop = <&anatop>;
677 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
678 reg = <0x020ca000 0x1000>;
681 fsl,anatop = <&anatop>;
685 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
686 reg = <0x020cc000 0x4000>;
688 snvs_rtc: snvs-rtc-lp {
689 compatible = "fsl,sec-v4.0-mon-rtc-lp";
691 offset = <0x34>;
695 snvs_poweroff: snvs-poweroff {
696 compatible = "syscon-poweroff";
698 offset = <0x38>;
703 snvs_pwrkey: snvs-powerkey {
704 compatible = "fsl,sec-v4.0-pwrkey";
708 wakeup-source;
713 reg = <0x020d0000 0x4000>;
718 reg = <0x020d4000 0x4000>;
723 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
724 reg = <0x020d8000 0x4000>;
727 #reset-cells = <1>;
731 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
732 reg = <0x020dc000 0x4000>;
733 interrupt-controller;
734 #interrupt-cells = <3>;
736 interrupt-parent = <&intc>;
740 compatible = "fsl,imx6sx-iomuxc";
741 reg = <0x020e0000 0x4000>;
744 gpr: iomuxc-gpr@020e4000 {
745 compatible = "fsl,imx6sx-iomuxc-gpr",
746 "fsl,imx6q-iomuxc-gpr", "syscon";
747 reg = <0x020e4000 0x4000>;
751 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
752 reg = <0x020ec000 0x4000>;
756 clock-names = "ipg", "ahb";
757 #dma-cells = <3>;
759 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
763 aips2: aips-bus@02100000 {
764 compatible = "fsl,aips-bus", "simple-bus";
765 #address-cells = <1>;
766 #size-cells = <1>;
767 reg = <0x02100000 0x100000>;
771 compatible = "fsl,sec-v4.0";
772 fsl,sec-era = <4>;
773 #address-cells = <1>;
774 #size-cells = <1>;
775 reg = <0x2100000 0x10000>;
777 interrupt-parent = <&intc>;
782 clock-names = "mem", "aclk", "ipg", "emi_slow";
785 compatible = "fsl,sec-v4.0-job-ring";
786 reg = <0x1000 0x1000>;
791 compatible = "fsl,sec-v4.0-job-ring";
792 reg = <0x2000 0x1000>;
798 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
799 reg = <0x02184000 0x200>;
804 fsl,anatop = <&anatop>;
805 ahb-burst-config = <0x0>;
806 tx-burst-size-dword = <0x10>;
807 rx-burst-size-dword = <0x10>;
812 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
813 reg = <0x02184200 0x200>;
818 ahb-burst-config = <0x0>;
819 tx-burst-size-dword = <0x10>;
820 rx-burst-size-dword = <0x10>;
825 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
826 reg = <0x02184400 0x200>;
831 fsl,anatop = <&anatop>;
833 ahb-burst-config = <0x0>;
834 tx-burst-size-dword = <0x10>;
835 rx-burst-size-dword = <0x10>;
840 #index-cells = <1>;
841 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
842 reg = <0x02184800 0x200>;
847 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
848 reg = <0x02188000 0x4000>;
856 clock-names = "ipg", "ahb", "ptp",
858 fsl,num-tx-queues=<3>;
859 fsl,num-rx-queues=<3>;
864 reg = <0x0218c000 0x4000>;
873 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
874 reg = <0x02190000 0x4000>;
879 clock-names = "ipg", "ahb", "per";
880 bus-width = <4>;
885 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
886 reg = <0x02194000 0x4000>;
891 clock-names = "ipg", "ahb", "per";
892 bus-width = <4>;
897 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
898 reg = <0x02198000 0x4000>;
903 clock-names = "ipg", "ahb", "per";
904 bus-width = <4>;
909 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
910 reg = <0x0219c000 0x4000>;
915 clock-names = "ipg", "ahb", "per";
916 bus-width = <4>;
921 #address-cells = <1>;
922 #size-cells = <0>;
923 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
924 reg = <0x021a0000 0x4000>;
931 #address-cells = <1>;
932 #size-cells = <0>;
933 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
934 reg = <0x021a4000 0x4000>;
941 #address-cells = <1>;
942 #size-cells = <0>;
943 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
944 reg = <0x021a8000 0x4000>;
951 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
952 reg = <0x021b0000 0x4000>;
956 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
957 reg = <0x021b4000 0x4000>;
965 clock-names = "ipg", "ahb", "ptp",
971 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
972 reg = <0x021b8000 0x4000>;
978 compatible = "fsl,imx6sx-ocotp", "syscon";
979 reg = <0x021bc000 0x4000>;
984 compatible = "fsl,imx6sx-sai";
985 reg = <0x021d4000 0x4000>;
990 clock-names = "bus", "mclk1", "mclk2", "mclk3";
991 dma-names = "rx", "tx";
997 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
998 reg = <0x021d8000 0x4000>;
1003 compatible = "fsl,imx6sx-sai";
1004 reg = <0x021dc000 0x4000>;
1009 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1010 dma-names = "rx", "tx";
1016 #address-cells = <1>;
1017 #size-cells = <0>;
1018 compatible = "fsl,imx6sx-qspi";
1019 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1020 reg-names = "QuadSPI", "QuadSPI-memory";
1024 clock-names = "qspi_en", "qspi";
1029 #address-cells = <1>;
1030 #size-cells = <0>;
1031 compatible = "fsl,imx6sx-qspi";
1032 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1033 reg-names = "QuadSPI", "QuadSPI-memory";
1037 clock-names = "qspi_en", "qspi";
1042 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1043 reg = <0x021e8000 0x4000>;
1047 clock-names = "ipg", "per";
1049 dma-names = "rx", "tx";
1054 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1055 reg = <0x021ec000 0x4000>;
1059 clock-names = "ipg", "per";
1061 dma-names = "rx", "tx";
1066 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1067 reg = <0x021f0000 0x4000>;
1071 clock-names = "ipg", "per";
1073 dma-names = "rx", "tx";
1078 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1079 reg = <0x021f4000 0x4000>;
1083 clock-names = "ipg", "per";
1085 dma-names = "rx", "tx";
1090 #address-cells = <1>;
1091 #size-cells = <0>;
1092 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1093 reg = <0x021f8000 0x4000>;
1100 aips3: aips-bus@02200000 {
1101 compatible = "fsl,aips-bus", "simple-bus";
1102 #address-cells = <1>;
1103 #size-cells = <1>;
1104 reg = <0x02200000 0x100000>;
1107 spba-bus@02200000 {
1108 compatible = "fsl,spba-bus", "simple-bus";
1109 #address-cells = <1>;
1110 #size-cells = <1>;
1111 reg = <0x02240000 0x40000>;
1115 reg = <0x02214000 0x4000>;
1120 clock-names = "disp-axi", "csi_mclk", "dcic";
1125 reg = <0x02218000 0x4000>;
1129 clock-names = "pxp-axi", "disp-axi";
1134 reg = <0x0221c000 0x4000>;
1139 clock-names = "disp-axi", "csi_mclk", "dcic";
1144 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1145 reg = <0x02220000 0x4000>;
1150 clock-names = "pix", "axi", "disp_axi";
1155 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1156 reg = <0x02224000 0x4000>;
1161 clock-names = "pix", "axi", "disp_axi";
1166 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1167 reg-names = "vadc-vafe", "vadc-vdec";
1170 clock-names = "vadc", "csi";
1176 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1177 reg = <0x02280000 0x4000>;
1180 clock-names = "adc";
1181 fsl,adck-max-frequency = <30000000>, <40000000>,
1187 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1188 reg = <0x02284000 0x4000>;
1191 clock-names = "adc";
1192 fsl,adck-max-frequency = <30000000>, <40000000>,
1198 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1199 reg = <0x02288000 0x4000>;
1206 #address-cells = <1>;
1207 #size-cells = <0>;
1208 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1209 reg = <0x0228c000 0x4000>;
1213 clock-names = "ipg", "per";
1218 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1219 reg = <0x022a0000 0x4000>;
1223 clock-names = "ipg", "per";
1225 dma-names = "rx", "tx";
1230 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1231 reg = <0x022a4000 0x4000>;
1235 clock-names = "ipg", "per";
1236 #pwm-cells = <2>;
1240 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1241 reg = <0x022a8000 0x4000>;
1245 clock-names = "ipg", "per";
1246 #pwm-cells = <2>;
1250 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1251 reg = <0x022ac000 0x4000>;
1255 clock-names = "ipg", "per";
1256 #pwm-cells = <2>;
1260 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1261 reg = <0x0022b0000 0x4000>;
1265 clock-names = "ipg", "per";
1266 #pwm-cells = <2>;
1271 compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1272 reg = <0x08ffc000 0x4000>; /* DBI */
1273 #address-cells = <3>;
1274 #size-cells = <2>;
1280 /* non-prefetchable memory */
1282 num-lanes = <1>;
1288 clock-names = "pcie_ref_125m", "pcie_axi",
1294 gpu-subsystem {
1295 compatible = "fsl,imx-gpu-subsystem";