Lines Matching +full:0 +full:x021bc000
54 #size-cells = <0>;
56 cpu0: cpu@0 {
59 reg = <0>;
92 reg = <0x00a01000 0x1000>,
93 <0x00a00100 0x100>;
99 #size-cells = <0>;
101 ckil: clock@0 {
103 reg = <0>;
104 #clock-cells = <0>;
112 #clock-cells = <0>;
120 #clock-cells = <0>;
121 clock-frequency = <0>;
128 #clock-cells = <0>;
129 clock-frequency = <0>;
148 reg = <0x00900000 0x20000>;
154 reg = <0x00a02000 0x1000>;
164 reg = <0x01800000 0x4000>;
174 reg = <0x01804000 0x2000>;
189 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
200 dmas = <&dma_apbh 0>;
209 reg = <0x02000000 0x100000>;
216 reg = <0x02000000 0x40000>;
221 reg = <0x02004000 0x4000>;
223 dmas = <&sdma 14 18 0>,
224 <&sdma 15 18 0>;
229 <&clks 0>, <&clks 0>, <&clks 0>,
231 <&clks 0>, <&clks 0>,
243 #size-cells = <0>;
245 reg = <0x02008000 0x4000>;
255 #size-cells = <0>;
257 reg = <0x0200c000 0x4000>;
267 #size-cells = <0>;
269 reg = <0x02010000 0x4000>;
279 #size-cells = <0>;
281 reg = <0x02014000 0x4000>;
291 reg = <0x02020000 0x4000>;
296 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
302 reg = <0x02024000 0x4000>;
315 #sound-dai-cells = <0>;
317 reg = <0x02028000 0x4000>;
322 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
329 #sound-dai-cells = <0>;
331 reg = <0x0202c000 0x4000>;
336 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
343 #sound-dai-cells = <0>;
345 reg = <0x02030000 0x4000>;
350 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
357 reg = <0x02034000 0x4000>;
375 reg = <0x02080000 0x4000>;
385 reg = <0x02084000 0x4000>;
395 reg = <0x02088000 0x4000>;
405 reg = <0x0208c000 0x4000>;
415 reg = <0x02090000 0x4000>;
425 reg = <0x02094000 0x4000>;
435 reg = <0x02098000 0x4000>;
444 reg = <0x0209c000 0x4000>;
451 gpio-ranges = <&iomuxc 0 5 26>;
456 reg = <0x020a0000 0x4000>;
463 gpio-ranges = <&iomuxc 0 31 20>;
468 reg = <0x020a4000 0x4000>;
475 gpio-ranges = <&iomuxc 0 51 29>;
480 reg = <0x020a8000 0x4000>;
487 gpio-ranges = <&iomuxc 0 80 32>;
492 reg = <0x020ac000 0x4000>;
499 gpio-ranges = <&iomuxc 0 112 24>;
504 reg = <0x020b0000 0x4000>;
511 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
516 reg = <0x020b4000 0x4000>;
523 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
528 reg = <0x020b8000 0x4000>;
536 reg = <0x020bc000 0x4000>;
543 reg = <0x020c0000 0x4000>;
551 reg = <0x020c4000 0x4000>;
562 reg = <0x020c8000 0x1000>;
573 anatop-reg-offset = <0x110>;
587 anatop-reg-offset = <0x120>;
590 anatop-min-bit-val = <0>;
601 anatop-reg-offset = <0x130>;
604 anatop-min-bit-val = <0>;
615 anatop-reg-offset = <0x140>;
616 anatop-vol-bit-shift = <0>;
618 anatop-delay-reg-offset = <0x170>;
631 anatop-reg-offset = <0x140>;
634 anatop-delay-reg-offset = <0x170>;
648 anatop-reg-offset = <0x140>;
651 anatop-delay-reg-offset = <0x170>;
670 reg = <0x020c9000 0x1000>;
678 reg = <0x020ca000 0x1000>;
685 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
686 reg = <0x020cc000 0x4000>;
689 compatible = "fsl,sec-v4.0-mon-rtc-lp";
691 offset = <0x34>;
698 offset = <0x38>;
699 mask = <0x60>;
704 compatible = "fsl,sec-v4.0-pwrkey";
713 reg = <0x020d0000 0x4000>;
718 reg = <0x020d4000 0x4000>;
724 reg = <0x020d8000 0x4000>;
732 reg = <0x020dc000 0x4000>;
741 reg = <0x020e0000 0x4000>;
747 reg = <0x020e4000 0x4000>;
752 reg = <0x020ec000 0x4000>;
767 reg = <0x02100000 0x100000>;
771 compatible = "fsl,sec-v4.0";
775 reg = <0x2100000 0x10000>;
776 ranges = <0 0x2100000 0x10000>;
785 compatible = "fsl,sec-v4.0-job-ring";
786 reg = <0x1000 0x1000>;
791 compatible = "fsl,sec-v4.0-job-ring";
792 reg = <0x2000 0x1000>;
799 reg = <0x02184000 0x200>;
803 fsl,usbmisc = <&usbmisc 0>;
805 ahb-burst-config = <0x0>;
806 tx-burst-size-dword = <0x10>;
807 rx-burst-size-dword = <0x10>;
813 reg = <0x02184200 0x200>;
818 ahb-burst-config = <0x0>;
819 tx-burst-size-dword = <0x10>;
820 rx-burst-size-dword = <0x10>;
826 reg = <0x02184400 0x200>;
833 ahb-burst-config = <0x0>;
834 tx-burst-size-dword = <0x10>;
835 rx-burst-size-dword = <0x10>;
842 reg = <0x02184800 0x200>;
848 reg = <0x02188000 0x4000>;
864 reg = <0x0218c000 0x4000>;
874 reg = <0x02190000 0x4000>;
886 reg = <0x02194000 0x4000>;
898 reg = <0x02198000 0x4000>;
910 reg = <0x0219c000 0x4000>;
922 #size-cells = <0>;
924 reg = <0x021a0000 0x4000>;
932 #size-cells = <0>;
934 reg = <0x021a4000 0x4000>;
942 #size-cells = <0>;
944 reg = <0x021a8000 0x4000>;
952 reg = <0x021b0000 0x4000>;
957 reg = <0x021b4000 0x4000>;
972 reg = <0x021b8000 0x4000>;
979 reg = <0x021bc000 0x4000>;
985 reg = <0x021d4000 0x4000>;
989 <&clks 0>, <&clks 0>;
992 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
998 reg = <0x021d8000 0x4000>;
1004 reg = <0x021dc000 0x4000>;
1008 <&clks 0>, <&clks 0>;
1011 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
1017 #size-cells = <0>;
1019 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1030 #size-cells = <0>;
1032 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1043 reg = <0x021e8000 0x4000>;
1048 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1055 reg = <0x021ec000 0x4000>;
1060 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1067 reg = <0x021f0000 0x4000>;
1072 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1079 reg = <0x021f4000 0x4000>;
1084 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1091 #size-cells = <0>;
1093 reg = <0x021f8000 0x4000>;
1104 reg = <0x02200000 0x100000>;
1111 reg = <0x02240000 0x40000>;
1115 reg = <0x02214000 0x4000>;
1125 reg = <0x02218000 0x4000>;
1134 reg = <0x0221c000 0x4000>;
1145 reg = <0x02220000 0x4000>;
1156 reg = <0x02224000 0x4000>;
1166 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1177 reg = <0x02280000 0x4000>;
1188 reg = <0x02284000 0x4000>;
1199 reg = <0x02288000 0x4000>;
1207 #size-cells = <0>;
1209 reg = <0x0228c000 0x4000>;
1219 reg = <0x022a0000 0x4000>;
1224 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1231 reg = <0x022a4000 0x4000>;
1241 reg = <0x022a8000 0x4000>;
1251 reg = <0x022ac000 0x4000>;
1261 reg = <0x0022b0000 0x4000>;
1270 pcie: pcie@0x08000000 {
1272 reg = <0x08ffc000 0x4000>; /* DBI */
1277 ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000
1279 0x81000000 0 0 0x08f80000 0 0x00010000
1281 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>;