Lines Matching +full:imx53 +full:- +full:rtc
9 * http://www.opensource.org/licenses/gpl-license.html
13 #include <dt-bindings/clock/imx6qdl-clock.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
52 #address-cells = <1>;
53 #size-cells = <0>;
56 compatible = "fsl,imx-ckil", "fixed-clock";
57 #clock-cells = <0>;
58 clock-frequency = <32768>;
62 compatible = "fsl,imx-ckih1", "fixed-clock";
63 #clock-cells = <0>;
64 clock-frequency = <0>;
68 compatible = "fsl,imx-osc", "fixed-clock";
69 #clock-cells = <0>;
70 clock-frequency = <24000000>;
75 #address-cells = <1>;
76 #size-cells = <1>;
77 compatible = "simple-bus";
78 interrupt-parent = <&gpc>;
81 dma_apbh: dma-apbh@00110000 {
82 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
88 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
89 #dma-cells = <1>;
90 dma-channels = <4>;
94 gpmi: gpmi-nand@00112000 {
95 compatible = "fsl,imx6q-gpmi-nand";
96 #address-cells = <1>;
97 #size-cells = <1>;
99 reg-names = "gpmi-nand", "bch";
101 interrupt-names = "bch";
107 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
110 dma-names = "rx-tx";
115 #address-cells = <1>;
116 #size-cells = <0>;
122 clock-names = "iahb", "isfr";
129 remote-endpoint = <&ipu1_di0_hdmi>;
137 remote-endpoint = <&ipu1_di1_hdmi>;
149 clock-names = "bus", "core", "shader";
150 power-domains = <&gpc 1>;
159 clock-names = "bus", "core";
160 power-domains = <&gpc 1>;
164 compatible = "arm,cortex-a9-twd-timer";
167 interrupt-parent = <&intc>;
171 intc: interrupt-controller@00a01000 {
172 compatible = "arm,cortex-a9-gic";
173 #interrupt-cells = <3>;
174 interrupt-controller;
177 interrupt-parent = <&intc>;
180 L2: l2-cache@00a02000 {
181 compatible = "arm,pl310-cache";
184 cache-unified;
185 cache-level = <2>;
186 arm,tag-latency = <4 2 3>;
187 arm,data-latency = <4 2 3>;
188 arm,shared-override;
192 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
195 reg-names = "dbi", "config";
196 #address-cells = <3>;
197 #size-cells = <2>;
200 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
201 num-lanes = <1>;
203 interrupt-names = "msi";
204 #interrupt-cells = <1>;
205 interrupt-map-mask = <0 0 0 0x7>;
206 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
213 clock-names = "pcie", "pcie_bus", "pcie_phy";
218 compatible = "arm,cortex-a9-pmu";
222 aips-bus@02000000 { /* AIPS1 */
223 compatible = "fsl,aips-bus", "simple-bus";
224 #address-cells = <1>;
225 #size-cells = <1>;
229 spba-bus@02000000 {
230 compatible = "fsl,spba-bus", "simple-bus";
231 #address-cells = <1>;
232 #size-cells = <1>;
237 compatible = "fsl,imx35-spdif";
242 dma-names = "rx", "tx";
248 clock-names = "core", "rxtx0",
257 #address-cells = <1>;
258 #size-cells = <0>;
259 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
264 clock-names = "ipg", "per";
266 dma-names = "rx", "tx";
271 #address-cells = <1>;
272 #size-cells = <0>;
273 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
278 clock-names = "ipg", "per";
280 dma-names = "rx", "tx";
285 #address-cells = <1>;
286 #size-cells = <0>;
287 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
292 clock-names = "ipg", "per";
294 dma-names = "rx", "tx";
299 #address-cells = <1>;
300 #size-cells = <0>;
301 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
306 clock-names = "ipg", "per";
308 dma-names = "rx", "tx";
313 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
318 clock-names = "ipg", "per";
320 dma-names = "rx", "tx";
325 #sound-dai-cells = <0>;
326 compatible = "fsl,imx35-esai";
334 clock-names = "core", "mem", "extal", "fsys", "spba";
336 dma-names = "rx", "tx";
341 #sound-dai-cells = <0>;
342 compatible = "fsl,imx6q-ssi",
343 "fsl,imx51-ssi";
348 clock-names = "ipg", "baud";
351 dma-names = "rx", "tx";
352 fsl,fifo-depth = <15>;
357 #sound-dai-cells = <0>;
358 compatible = "fsl,imx6q-ssi",
359 "fsl,imx51-ssi";
364 clock-names = "ipg", "baud";
367 dma-names = "rx", "tx";
368 fsl,fifo-depth = <15>;
373 #sound-dai-cells = <0>;
374 compatible = "fsl,imx6q-ssi",
375 "fsl,imx51-ssi";
380 clock-names = "ipg", "baud";
383 dma-names = "rx", "tx";
384 fsl,fifo-depth = <15>;
389 compatible = "fsl,imx53-asrc";
399 clock-names = "mem", "ipg", "asrck_0",
406 dma-names = "rxa", "rxb", "rxc",
408 fsl,asrc-rate = <48000>;
409 fsl,asrc-width = <16>;
423 interrupt-names = "bit", "jpeg";
426 clock-names = "per", "ahb";
427 power-domains = <&gpc 1>;
437 #pwm-cells = <2>;
438 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
443 clock-names = "ipg", "per";
448 #pwm-cells = <2>;
449 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
454 clock-names = "ipg", "per";
459 #pwm-cells = <2>;
460 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
465 clock-names = "ipg", "per";
470 #pwm-cells = <2>;
471 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
476 clock-names = "ipg", "per";
481 compatible = "fsl,imx6q-flexcan";
486 clock-names = "ipg", "per";
491 compatible = "fsl,imx6q-flexcan";
496 clock-names = "ipg", "per";
501 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
507 clock-names = "ipg", "per", "osc_per";
511 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
515 gpio-controller;
516 #gpio-cells = <2>;
517 interrupt-controller;
518 #interrupt-cells = <2>;
522 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
526 gpio-controller;
527 #gpio-cells = <2>;
528 interrupt-controller;
529 #interrupt-cells = <2>;
533 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
537 gpio-controller;
538 #gpio-cells = <2>;
539 interrupt-controller;
540 #interrupt-cells = <2>;
544 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
548 gpio-controller;
549 #gpio-cells = <2>;
550 interrupt-controller;
551 #interrupt-cells = <2>;
555 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
559 gpio-controller;
560 #gpio-cells = <2>;
561 interrupt-controller;
562 #interrupt-cells = <2>;
566 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
570 gpio-controller;
571 #gpio-cells = <2>;
572 interrupt-controller;
573 #interrupt-cells = <2>;
577 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
581 gpio-controller;
582 #gpio-cells = <2>;
583 interrupt-controller;
584 #interrupt-cells = <2>;
588 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
596 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
603 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
611 compatible = "fsl,imx6q-ccm";
615 #clock-cells = <1>;
619 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
625 regulator-1p1 {
626 compatible = "fsl,anatop-regulator";
627 regulator-name = "vdd1p1";
628 regulator-min-microvolt = <800000>;
629 regulator-max-microvolt = <1375000>;
630 regulator-always-on;
631 anatop-reg-offset = <0x110>;
632 anatop-vol-bit-shift = <8>;
633 anatop-vol-bit-width = <5>;
634 anatop-min-bit-val = <4>;
635 anatop-min-voltage = <800000>;
636 anatop-max-voltage = <1375000>;
639 regulator-3p0 {
640 compatible = "fsl,anatop-regulator";
641 regulator-name = "vdd3p0";
642 regulator-min-microvolt = <2800000>;
643 regulator-max-microvolt = <3150000>;
644 regulator-always-on;
645 anatop-reg-offset = <0x120>;
646 anatop-vol-bit-shift = <8>;
647 anatop-vol-bit-width = <5>;
648 anatop-min-bit-val = <0>;
649 anatop-min-voltage = <2625000>;
650 anatop-max-voltage = <3400000>;
653 regulator-2p5 {
654 compatible = "fsl,anatop-regulator";
655 regulator-name = "vdd2p5";
656 regulator-min-microvolt = <2000000>;
657 regulator-max-microvolt = <2750000>;
658 regulator-always-on;
659 anatop-reg-offset = <0x130>;
660 anatop-vol-bit-shift = <8>;
661 anatop-vol-bit-width = <5>;
662 anatop-min-bit-val = <0>;
663 anatop-min-voltage = <2000000>;
664 anatop-max-voltage = <2750000>;
667 reg_arm: regulator-vddcore {
668 compatible = "fsl,anatop-regulator";
669 regulator-name = "vddarm";
670 regulator-min-microvolt = <725000>;
671 regulator-max-microvolt = <1450000>;
672 regulator-always-on;
673 anatop-reg-offset = <0x140>;
674 anatop-vol-bit-shift = <0>;
675 anatop-vol-bit-width = <5>;
676 anatop-delay-reg-offset = <0x170>;
677 anatop-delay-bit-shift = <24>;
678 anatop-delay-bit-width = <2>;
679 anatop-min-bit-val = <1>;
680 anatop-min-voltage = <725000>;
681 anatop-max-voltage = <1450000>;
684 reg_pu: regulator-vddpu {
685 compatible = "fsl,anatop-regulator";
686 regulator-name = "vddpu";
687 regulator-min-microvolt = <725000>;
688 regulator-max-microvolt = <1450000>;
689 regulator-enable-ramp-delay = <150>;
690 anatop-reg-offset = <0x140>;
691 anatop-vol-bit-shift = <9>;
692 anatop-vol-bit-width = <5>;
693 anatop-delay-reg-offset = <0x170>;
694 anatop-delay-bit-shift = <26>;
695 anatop-delay-bit-width = <2>;
696 anatop-min-bit-val = <1>;
697 anatop-min-voltage = <725000>;
698 anatop-max-voltage = <1450000>;
701 reg_soc: regulator-vddsoc {
702 compatible = "fsl,anatop-regulator";
703 regulator-name = "vddsoc";
704 regulator-min-microvolt = <725000>;
705 regulator-max-microvolt = <1450000>;
706 regulator-always-on;
707 anatop-reg-offset = <0x140>;
708 anatop-vol-bit-shift = <18>;
709 anatop-vol-bit-width = <5>;
710 anatop-delay-reg-offset = <0x170>;
711 anatop-delay-bit-shift = <28>;
712 anatop-delay-bit-width = <2>;
713 anatop-min-bit-val = <1>;
714 anatop-min-voltage = <725000>;
715 anatop-max-voltage = <1450000>;
720 compatible = "fsl,imx6q-tempmon";
723 fsl,tempmon-data = <&ocotp>;
728 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
736 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
744 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
747 snvs_rtc: snvs-rtc-lp {
748 compatible = "fsl,sec-v4.0-mon-rtc-lp";
755 snvs_poweroff: snvs-poweroff {
756 compatible = "syscon-poweroff";
775 compatible = "fsl,imx6q-src", "fsl,imx51-src";
779 #reset-cells = <1>;
783 compatible = "fsl,imx6q-gpc";
785 interrupt-controller;
786 #interrupt-cells = <3>;
789 interrupt-parent = <&intc>;
790 pu-supply = <®_pu>;
797 #power-domain-cells = <1>;
800 gpr: iomuxc-gpr@020e0000 {
801 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
806 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
811 #address-cells = <1>;
812 #size-cells = <0>;
813 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
817 lvds-channel@0 {
818 #address-cells = <1>;
819 #size-cells = <0>;
827 remote-endpoint = <&ipu1_di0_lvds0>;
835 remote-endpoint = <&ipu1_di1_lvds0>;
840 lvds-channel@1 {
841 #address-cells = <1>;
842 #size-cells = <0>;
850 remote-endpoint = <&ipu1_di0_lvds1>;
858 remote-endpoint = <&ipu1_di1_lvds1>;
875 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
880 clock-names = "ipg", "ahb";
881 #dma-cells = <3>;
882 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
886 aips-bus@02100000 { /* AIPS2 */
887 compatible = "fsl,aips-bus", "simple-bus";
888 #address-cells = <1>;
889 #size-cells = <1>;
894 compatible = "fsl,sec-v4.0";
895 fsl,sec-era = <4>;
896 #address-cells = <1>;
897 #size-cells = <1>;
904 clock-names = "mem", "aclk", "ipg", "emi_slow";
907 compatible = "fsl,sec-v4.0-job-ring";
913 compatible = "fsl,sec-v4.0-job-ring";
924 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
930 ahb-burst-config = <0x0>;
931 tx-burst-size-dword = <0x10>;
932 rx-burst-size-dword = <0x10>;
937 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
944 ahb-burst-config = <0x0>;
945 tx-burst-size-dword = <0x10>;
946 rx-burst-size-dword = <0x10>;
951 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
957 ahb-burst-config = <0x0>;
958 tx-burst-size-dword = <0x10>;
959 rx-burst-size-dword = <0x10>;
964 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
970 ahb-burst-config = <0x0>;
971 tx-burst-size-dword = <0x10>;
972 rx-burst-size-dword = <0x10>;
977 #index-cells = <1>;
978 compatible = "fsl,imx6q-usbmisc";
984 compatible = "fsl,imx6q-fec";
986 interrupts-extended =
992 clock-names = "ipg", "ahb", "ptp";
1004 compatible = "fsl,imx6q-usdhc";
1010 clock-names = "ipg", "ahb", "per";
1011 bus-width = <4>;
1016 compatible = "fsl,imx6q-usdhc";
1022 clock-names = "ipg", "ahb", "per";
1023 bus-width = <4>;
1028 compatible = "fsl,imx6q-usdhc";
1034 clock-names = "ipg", "ahb", "per";
1035 bus-width = <4>;
1040 compatible = "fsl,imx6q-usdhc";
1046 clock-names = "ipg", "ahb", "per";
1047 bus-width = <4>;
1052 #address-cells = <1>;
1053 #size-cells = <0>;
1054 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1062 #address-cells = <1>;
1063 #size-cells = <0>;
1064 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1072 #address-cells = <1>;
1073 #size-cells = <0>;
1074 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1086 compatible = "fsl,imx6q-mmdc";
1095 compatible = "fsl,imx6q-weim";
1102 compatible = "fsl,imx6q-ocotp", "syscon";
1118 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1128 #address-cells = <1>;
1129 #size-cells = <0>;
1134 #address-cells = <1>;
1135 #size-cells = <0>;
1141 remote-endpoint = <&ipu1_di0_mipi>;
1149 remote-endpoint = <&ipu1_di1_mipi>;
1161 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1166 clock-names = "ipg", "per";
1168 dma-names = "rx", "tx";
1173 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1178 clock-names = "ipg", "per";
1180 dma-names = "rx", "tx";
1185 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1190 clock-names = "ipg", "per";
1192 dma-names = "rx", "tx";
1197 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1202 clock-names = "ipg", "per";
1204 dma-names = "rx", "tx";
1210 #address-cells = <1>;
1211 #size-cells = <0>;
1212 compatible = "fsl,imx6q-ipu";
1219 clock-names = "bus", "di0", "di1";
1231 #address-cells = <1>;
1232 #size-cells = <0>;
1235 ipu1_di0_disp0: disp0-endpoint {
1238 ipu1_di0_hdmi: hdmi-endpoint {
1239 remote-endpoint = <&hdmi_mux_0>;
1242 ipu1_di0_mipi: mipi-endpoint {
1243 remote-endpoint = <&mipi_mux_0>;
1246 ipu1_di0_lvds0: lvds0-endpoint {
1247 remote-endpoint = <&lvds0_mux_0>;
1250 ipu1_di0_lvds1: lvds1-endpoint {
1251 remote-endpoint = <&lvds1_mux_0>;
1256 #address-cells = <1>;
1257 #size-cells = <0>;
1260 ipu1_di1_disp1: disp1-endpoint {
1263 ipu1_di1_hdmi: hdmi-endpoint {
1264 remote-endpoint = <&hdmi_mux_1>;
1267 ipu1_di1_mipi: mipi-endpoint {
1268 remote-endpoint = <&mipi_mux_1>;
1271 ipu1_di1_lvds0: lvds0-endpoint {
1272 remote-endpoint = <&lvds0_mux_1>;
1275 ipu1_di1_lvds1: lvds1-endpoint {
1276 remote-endpoint = <&lvds1_mux_1>;