arm/dts/imx6qdl.dtsi

53 		#size-cells = <0>;
57 			#clock-cells = <0>;
63 			#clock-cells = <0>;
64 			clock-frequency = <0>;
69 			#clock-cells = <0>;
83 			reg = <0x00110000 0x2000>;
84 			interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
85 				     <0 13 IRQ_TYPE_LEVEL_HIGH>,
86 				     <0 13 IRQ_TYPE_LEVEL_HIGH>,
87 				     <0 13 IRQ_TYPE_LEVEL_HIGH>;
98 			reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
100 			interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
109 			dmas = <&dma_apbh 0>;
116 			#size-cells = <0>;
117 			reg = <0x00120000 0x9000>;
118 			interrupts = <0 115 0x04>;
125 			port@0 {
126 				reg = <0>;
144 			reg = <0x00130000 0x4000>;
145 			interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
155 			reg = <0x00134000 0x4000>;
156 			interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
165 			reg = <0x00a00600 0x20>;
166 			interrupts = <1 13 0xf01>;
175 			reg = <0x00a01000 0x1000>,
176 			      <0x00a00100 0x100>;
182 			reg = <0x00a02000 0x1000>;
183 			interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
191 		pcie: pcie@0x01000000 {
193 			reg = <0x01ffc000 0x04000>,
194 			      <0x01f00000 0x80000>;
199 			ranges = <0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
200 				  0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
205 			interrupt-map-mask = <0 0 0 0x7>;
206 			interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
207 			                <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
208 			                <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
209 			                <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
219 			interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
226 			reg = <0x02000000 0x100000>;
233 				reg = <0x02000000 0x40000>;
238 					reg = <0x02004000 0x4000>;
239 					interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
240 					dmas = <&sdma 14 18 0>,
241 					       <&sdma 15 18 0>;
258 					#size-cells = <0>;
260 					reg = <0x02008000 0x4000>;
261 					interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
272 					#size-cells = <0>;
274 					reg = <0x0200c000 0x4000>;
275 					interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
286 					#size-cells = <0>;
288 					reg = <0x02010000 0x4000>;
289 					interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
300 					#size-cells = <0>;
302 					reg = <0x02014000 0x4000>;
303 					interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
314 					reg = <0x02020000 0x4000>;
315 					interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
319 					dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
325 					#sound-dai-cells = <0>;
327 					reg = <0x02024000 0x4000>;
328 					interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
335 					dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
341 					#sound-dai-cells = <0>;
344 					reg = <0x02028000 0x4000>;
345 					interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
349 					dmas = <&sdma 37 1 0>,
350 					       <&sdma 38 1 0>;
357 					#sound-dai-cells = <0>;
360 					reg = <0x0202c000 0x4000>;
361 					interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
365 					dmas = <&sdma 41 1 0>,
366 					       <&sdma 42 1 0>;
373 					#sound-dai-cells = <0>;
376 					reg = <0x02030000 0x4000>;
377 					interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
381 					dmas = <&sdma 45 1 0>,
382 					       <&sdma 46 1 0>;
390 					reg = <0x02034000 0x4000>;
391 					interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
393 						<&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
394 						<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
395 						<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
396 						<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
397 						<&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
414 					reg = <0x0203c000 0x4000>;
420 				reg = <0x02040000 0x3c000>;
421 				interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
422 					     <0 3 IRQ_TYPE_LEVEL_HIGH>;
433 				reg = <0x0207c000 0x4000>;
439 				reg = <0x02080000 0x4000>;
440 				interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
450 				reg = <0x02084000 0x4000>;
451 				interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
461 				reg = <0x02088000 0x4000>;
462 				interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
472 				reg = <0x0208c000 0x4000>;
473 				interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
482 				reg = <0x02090000 0x4000>;
483 				interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
492 				reg = <0x02094000 0x4000>;
493 				interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
502 				reg = <0x02098000 0x4000>;
503 				interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
512 				reg = <0x0209c000 0x4000>;
513 				interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
514 					     <0 67 IRQ_TYPE_LEVEL_HIGH>;
523 				reg = <0x020a0000 0x4000>;
524 				interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
525 					     <0 69 IRQ_TYPE_LEVEL_HIGH>;
534 				reg = <0x020a4000 0x4000>;
535 				interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
536 					     <0 71 IRQ_TYPE_LEVEL_HIGH>;
545 				reg = <0x020a8000 0x4000>;
546 				interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
547 					     <0 73 IRQ_TYPE_LEVEL_HIGH>;
556 				reg = <0x020ac000 0x4000>;
557 				interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
558 					     <0 75 IRQ_TYPE_LEVEL_HIGH>;
567 				reg = <0x020b0000 0x4000>;
568 				interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
569 					     <0 77 IRQ_TYPE_LEVEL_HIGH>;
578 				reg = <0x020b4000 0x4000>;
579 				interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
580 					     <0 79 IRQ_TYPE_LEVEL_HIGH>;
589 				reg = <0x020b8000 0x4000>;
590 				interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
597 				reg = <0x020bc000 0x4000>;
598 				interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
604 				reg = <0x020c0000 0x4000>;
605 				interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
612 				reg = <0x020c4000 0x4000>;
613 				interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
614 					     <0 88 IRQ_TYPE_LEVEL_HIGH>;
620 				reg = <0x020c8000 0x1000>;
621 				interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
622 					     <0 54 IRQ_TYPE_LEVEL_HIGH>,
623 					     <0 127 IRQ_TYPE_LEVEL_HIGH>;
631 					anatop-reg-offset = <0x110>;
645 					anatop-reg-offset = <0x120>;
648 					anatop-min-bit-val = <0>;
659 					anatop-reg-offset = <0x130>;
662 					anatop-min-bit-val = <0>;
673 					anatop-reg-offset = <0x140>;
674 					anatop-vol-bit-shift = <0>;
676 					anatop-delay-reg-offset = <0x170>;
690 					anatop-reg-offset = <0x140>;
693 					anatop-delay-reg-offset = <0x170>;
707 					anatop-reg-offset = <0x140>;
710 					anatop-delay-reg-offset = <0x170>;
721 				interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
729 				reg = <0x020c9000 0x1000>;
730 				interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
737 				reg = <0x020ca000 0x1000>;
738 				interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
744 				compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
745 				reg = <0x020cc000 0x4000>;
748 					compatible = "fsl,sec-v4.0-mon-rtc-lp";
750 					offset = <0x34>;
751 					interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
752 						     <0 20 IRQ_TYPE_LEVEL_HIGH>;
758 					offset = <0x38>;
759 					mask = <0x60>;
765 				reg = <0x020d0000 0x4000>;
766 				interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
770 				reg = <0x020d4000 0x4000>;
771 				interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
776 				reg = <0x020d8000 0x4000>;
777 				interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
778 					     <0 96 IRQ_TYPE_LEVEL_HIGH>;
784 				reg = <0x020dc000 0x4000>;
787 				interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
788 					     <0 90 IRQ_TYPE_LEVEL_HIGH>;
802 				reg = <0x020e0000 0x38>;
807 				reg = <0x020e0000 0x4000>;
812 				#size-cells = <0>;
817 				lvds-channel@0 {
819 					#size-cells = <0>;
820 					reg = <0>;
823 					port@0 {
824 						reg = <0>;
842 					#size-cells = <0>;
846 					port@0 {
847 						reg = <0>;
865 				reg = <0x020e4000 0x4000>;
866 				interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
870 				reg = <0x020e8000 0x4000>;
871 				interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
876 				reg = <0x020ec000 0x4000>;
877 				interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
890 			reg = <0x02100000 0x100000>;
894 				compatible = "fsl,sec-v4.0";
898 				reg = <0x2100000 0x10000>;
899 				ranges = <0 0x2100000 0x10000>;
907 					compatible = "fsl,sec-v4.0-job-ring";
908 					reg = <0x1000 0x1000>;
913 					compatible = "fsl,sec-v4.0-job-ring";
914 					reg = <0x2000 0x1000>;
920 				reg = <0x0217c000 0x4000>;
925 				reg = <0x02184000 0x200>;
926 				interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
929 				fsl,usbmisc = <&usbmisc 0>;
930 				ahb-burst-config = <0x0>;
931 				tx-burst-size-dword = <0x10>;
932 				rx-burst-size-dword = <0x10>;
938 				reg = <0x02184200 0x200>;
939 				interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
944 				ahb-burst-config = <0x0>;
945 				tx-burst-size-dword = <0x10>;
946 				rx-burst-size-dword = <0x10>;
952 				reg = <0x02184400 0x200>;
953 				interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
957 				ahb-burst-config = <0x0>;
958 				tx-burst-size-dword = <0x10>;
959 				rx-burst-size-dword = <0x10>;
965 				reg = <0x02184600 0x200>;
966 				interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
970 				ahb-burst-config = <0x0>;
971 				tx-burst-size-dword = <0x10>;
972 				rx-burst-size-dword = <0x10>;
979 				reg = <0x02184800 0x200>;
985 				reg = <0x02188000 0x4000>;
987 					<&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
988 					<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
997 				reg = <0x0218c000 0x4000>;
998 				interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
999 					     <0 117 IRQ_TYPE_LEVEL_HIGH>,
1000 					     <0 126 IRQ_TYPE_LEVEL_HIGH>;
1005 				reg = <0x02190000 0x4000>;
1006 				interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1017 				reg = <0x02194000 0x4000>;
1018 				interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1029 				reg = <0x02198000 0x4000>;
1030 				interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1041 				reg = <0x0219c000 0x4000>;
1042 				interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1053 				#size-cells = <0>;
1055 				reg = <0x021a0000 0x4000>;
1056 				interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1063 				#size-cells = <0>;
1065 				reg = <0x021a4000 0x4000>;
1066 				interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1073 				#size-cells = <0>;
1075 				reg = <0x021a8000 0x4000>;
1076 				interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1082 				reg = <0x021ac000 0x4000>;
1087 				reg = <0x021b0000 0x4000>;
1091 				reg = <0x021b4000 0x4000>;
1096 				reg = <0x021b8000 0x4000>;
1097 				interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1103 				reg = <0x021bc000 0x4000>;
1108 				reg = <0x021d0000 0x4000>;
1109 				interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1113 				reg = <0x021d4000 0x4000>;
1114 				interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1119 				reg = <0x021d8000 0x4000>;
1124 				reg = <0x021dc000 0x4000>;
1129 				#size-cells = <0>;
1130 				reg = <0x021e0000 0x4000>;
1135 					#size-cells = <0>;
1137 					port@0 {
1138 						reg = <0>;
1156 				reg = <0x021e4000 0x4000>;
1157 				interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1162 				reg = <0x021e8000 0x4000>;
1163 				interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1167 				dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1174 				reg = <0x021ec000 0x4000>;
1175 				interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1179 				dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1186 				reg = <0x021f0000 0x4000>;
1187 				interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1191 				dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1198 				reg = <0x021f4000 0x4000>;
1199 				interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1203 				dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1211 			#size-cells = <0>;
1213 			reg = <0x02400000 0x400000>;
1214 			interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1215 				     <0 5 IRQ_TYPE_LEVEL_HIGH>;
1222 			ipu1_csi0: port@0 {
1223 				reg = <0>;
1232 				#size-cells = <0>;
1257 				#size-cells = <0>;