arm/dts/imx6q.dtsi

11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include "imx6q-pinfunc.h"
22 		#address-cells = <1>;
23 		#size-cells = <0>;
26 			compatible = "arm,cortex-a9";
29 			next-level-cache = <&L2>;
30 			operating-points = <
38 			fsl,soc-operating-points = <
39 				/* ARM kHz  SOC-PU uV */
46 			clock-latency = <61036>; /* two CLK32 periods */
52 			clock-names = "arm", "pll2_pfd2_396m", "step",
54 			arm-supply = <&reg_arm>;
55 			pu-supply = <&reg_pu>;
56 			soc-supply = <&reg_soc>;
60 			compatible = "arm,cortex-a9";
63 			next-level-cache = <&L2>;
67 			compatible = "arm,cortex-a9";
70 			next-level-cache = <&L2>;
74 			compatible = "arm,cortex-a9";
77 			next-level-cache = <&L2>;
81 	soc {
83 			compatible = "mmio-sram";
88 		aips-bus@02000000 { /* AIPS1 */
89 			spba-bus@02000000 {
91 					#address-cells = <1>;
92 					#size-cells = <0>;
93 					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
98 					clock-names = "ipg", "per";
100 					dma-names = "rx", "tx";
106 				compatible = "fsl,imx6q-iomuxc";
111 			compatible = "fsl,imx6q-ahci";
117 			clock-names = "sata", "sata_ref", "ahb";
127 			clock-names = "bus", "core";
128 			power-domains = <&gpc 1>;
132 			#address-cells = <1>;
133 			#size-cells = <0>;
134 			compatible = "fsl,imx6q-ipu";
141 			clock-names = "bus", "di0", "di1";
153 				#address-cells = <1>;
154 				#size-cells = <0>;
157 				ipu2_di0_disp0: disp0-endpoint {
160 				ipu2_di0_hdmi: hdmi-endpoint {
161 					remote-endpoint = <&hdmi_mux_2>;
164 				ipu2_di0_mipi: mipi-endpoint {
165 					remote-endpoint = <&mipi_mux_2>;
168 				ipu2_di0_lvds0: lvds0-endpoint {
169 					remote-endpoint = <&lvds0_mux_2>;
172 				ipu2_di0_lvds1: lvds1-endpoint {
173 					remote-endpoint = <&lvds1_mux_2>;
178 				#address-cells = <1>;
179 				#size-cells = <0>;
182 				ipu2_di1_hdmi: hdmi-endpoint {
183 					remote-endpoint = <&hdmi_mux_3>;
186 				ipu2_di1_mipi: mipi-endpoint {
187 					remote-endpoint = <&mipi_mux_3>;
190 				ipu2_di1_lvds0: lvds0-endpoint {
191 					remote-endpoint = <&lvds0_mux_3>;
194 				ipu2_di1_lvds1: lvds1-endpoint {
195 					remote-endpoint = <&lvds1_mux_3>;
201 	display-subsystem {
202 		compatible = "fsl,imx-display-subsystem";
206 	gpu-subsystem {
207 		compatible = "fsl,imx-gpu-subsystem";
213 	compatible = "fsl,imx6q-hdmi";
219 			remote-endpoint = <&ipu2_di0_hdmi>;
227 			remote-endpoint = <&ipu2_di1_hdmi>;
237 	clock-names = "di0_pll", "di1_pll",
241 	lvds-channel@0 {
246 				remote-endpoint = <&ipu2_di0_lvds0>;
254 				remote-endpoint = <&ipu2_di1_lvds0>;
259 	lvds-channel@1 {
264 				remote-endpoint = <&ipu2_di0_lvds1>;
272 				remote-endpoint = <&ipu2_di1_lvds1>;
284 				remote-endpoint = <&ipu2_di0_mipi>;
292 				remote-endpoint = <&ipu2_di1_mipi>;
299 	compatible = "fsl,imx6q-vpu", "cnm,coda960";