arm/dts/hi6220.dtsi

7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/hi6220-clock.h>
12 	interrupt-parent = <&gic>;
13 	#address-cells = <2>;
14 	#size-cells = <2>;
17 		compatible = "arm,psci-0.2";
22 		#address-cells = <2>;
23 		#size-cells = <0>;
25 		cpu-map {
28 					cpu = <&cpu0>;
31 					cpu = <&cpu1>;
34 					cpu = <&cpu2>;
37 					cpu = <&cpu3>;
42 					cpu = <&cpu4>;
45 					cpu = <&cpu5>;
48 					cpu = <&cpu6>;
51 					cpu = <&cpu7>;
56 		cpu0: cpu@0 {
57 			compatible = "arm,cortex-a53", "arm,armv8";
58 			device_type = "cpu";
60 			enable-method = "psci";
63 		cpu1: cpu@1 {
64 			compatible = "arm,cortex-a53", "arm,armv8";
65 			device_type = "cpu";
67 			enable-method = "psci";
70 		cpu2: cpu@2 {
71 			compatible = "arm,cortex-a53", "arm,armv8";
72 			device_type = "cpu";
74 			enable-method = "psci";
77 		cpu3: cpu@3 {
78 			compatible = "arm,cortex-a53", "arm,armv8";
79 			device_type = "cpu";
81 			enable-method = "psci";
84 		cpu4: cpu@100 {
85 			compatible = "arm,cortex-a53", "arm,armv8";
86 			device_type = "cpu";
88 			enable-method = "psci";
91 		cpu5: cpu@101 {
92 			compatible = "arm,cortex-a53", "arm,armv8";
93 			device_type = "cpu";
95 			enable-method = "psci";
98 		cpu6: cpu@102 {
99 			compatible = "arm,cortex-a53", "arm,armv8";
100 			device_type = "cpu";
102 			enable-method = "psci";
105 		cpu7: cpu@103 {
106 			compatible = "arm,cortex-a53", "arm,armv8";
107 			device_type = "cpu";
109 			enable-method = "psci";
113 	gic: interrupt-controller@f6801000 {
114 		compatible = "arm,gic-400";
119 		#address-cells = <0>;
120 		#interrupt-cells = <3>;
121 		interrupt-controller;
122 		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
126 		compatible = "arm,armv8-timer";
127 		interrupt-parent = <&gic>;
128 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
129 			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
130 			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
131 			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
135 		compatible = "simple-bus";
136 		#address-cells = <2>;
137 		#size-cells = <2>;
141 			compatible = "hisilicon,hi6220-aoctrl", "syscon";
143 			#clock-cells = <1>;
147 			compatible = "hisilicon,hi6220-sysctrl", "syscon";
149 			#clock-cells = <1>;
150 			#reset-cells = <1>;
154 			compatible = "hisilicon,hi6220-mediactrl", "syscon";
156 			#clock-cells = <1>;
160 			compatible = "hisilicon,hi6220-pmctrl", "syscon";
162 			#clock-cells = <1>;
172 			clock-names = "uartclk", "apb_pclk";
182 			clock-names = "uartclk", "apb_pclk";
193 			clock-names = "uartclk", "apb_pclk";
204 			clock-names = "uartclk", "apb_pclk";
214 			clock-names = "uartclk", "apb_pclk";