Lines Matching refs:crg
85 crg: clock-reset-controller@8a22000 { label
86 compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";
122 clocks = <&crg HISTB_UART2_CLK>;
134 clocks = <&crg HISTB_I2C0_CLK>;
145 clocks = <&crg HISTB_I2C1_CLK>;
156 clocks = <&crg HISTB_I2C2_CLK>;
167 clocks = <&crg HISTB_I2C3_CLK>;
178 clocks = <&crg HISTB_I2C4_CLK>;
188 clocks = <&crg HISTB_SPI0_CLK>;
199 clocks = <&crg HISTB_MMC_CIU_CLK>,
200 <&crg HISTB_MMC_BIU_CLK>;
212 clocks = <&crg HISTB_APB_CLK>;
225 clocks = <&crg HISTB_APB_CLK>;
238 clocks = <&crg HISTB_APB_CLK>;
251 clocks = <&crg HISTB_APB_CLK>;
264 clocks = <&crg HISTB_APB_CLK>;
277 clocks = <&crg HISTB_APB_CLK>;
290 clocks = <&crg HISTB_APB_CLK>;
303 clocks = <&crg HISTB_APB_CLK>;
316 clocks = <&crg HISTB_APB_CLK>;
329 clocks = <&crg HISTB_APB_CLK>;
342 clocks = <&crg HISTB_APB_CLK>;
355 clocks = <&crg HISTB_APB_CLK>;
368 clocks = <&crg HISTB_APB_CLK>;
378 clocks = <&crg HISTB_ETH0_MAC_CLK>,
379 <&crg HISTB_ETH0_MACIF_CLK>;
381 resets = <&crg 0xcc 8>,
382 <&crg 0xcc 10>,
393 clocks = <&crg HISTB_ETH1_MAC_CLK>,
394 <&crg HISTB_ETH1_MACIF_CLK>;
396 resets = <&crg 0xcc 9>,
397 <&crg 0xcc 11>,