arm/dts/fsl-ls2080a.dtsi

4  * Copyright 2013-2015 Freescale Semiconductor, Inc.
6  * SPDX-License-Identifier:	GPL-2.0+
11 	interrupt-parent = <&gic>;
12 	#address-cells = <2>;
13 	#size-cells = <2>;
18 		      /* DRAM space - 1, size : 2 GB DRAM */
21 	gic: interrupt-controller@6000000 {
22 		compatible = "arm,gic-v3";
25 		#interrupt-cells = <3>;
26 		interrupt-controller;
31 		compatible = "arm,armv8-timer";
32 		interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
33 			     <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
34 			     <1 11 0x8>, /* Virtual PPI, active-low */
35 			     <1 10 0x8>; /* Hypervisor PPI, active-low */
42 		clock-frequency = <0>;	/* Updated by bootloader */
50 		clock-frequency = <0>; 	/* Updated by bootloader */
54 	fsl_mc: fsl-mc@80c000000 {
55 		compatible = "fsl,qoriq-mc";
61 		compatible = "fsl,vf610-dspi";
62 		#address-cells = <1>;
63 		#size-cells = <0>;
66 		num-cs = <6>;
70 		compatible = "fsl,vf610-qspi";
71 		#address-cells = <1>;
72 		#size-cells = <0>;
75 		reg-names = "QuadSPI", "QuadSPI-memory";
76 		num-cs = <4>;
80 		compatible = "fsl,layerscape-dwc3";
87 		compatible = "fsl,layerscape-dwc3";
94 		compatible = "fsl,ls-pcie", "snps,dw-pcie";
98 		reg-names = "dbi", "lut", "config";
99 		#address-cells = <3>;
100 		#size-cells = <2>;
102 		num-lanes = <4>;
103 		bus-range = <0x0 0xff>;
105 			  0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
109 		compatible = "fsl,ls-pcie", "snps,dw-pcie";
113 		reg-names = "dbi", "lut", "config";
114 		#address-cells = <3>;
115 		#size-cells = <2>;
117 		num-lanes = <4>;
118 		bus-range = <0x0 0xff>;
120 			  0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
124 		compatible = "fsl,ls-pcie", "snps,dw-pcie";
128 		reg-names = "dbi", "lut", "config";
129 		#address-cells = <3>;
130 		#size-cells = <2>;
132 		num-lanes = <8>;
133 		bus-range = <0x0 0xff>;
135 			  0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
139 		compatible = "fsl,ls-pcie", "snps,dw-pcie";
143 		reg-names = "dbi", "lut", "config";
144 		#address-cells = <3>;
145 		#size-cells = <2>;
147 		num-lanes = <4>;
148 		bus-range = <0x0 0xff>;
150 			  0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */