Lines Matching +full:0 +full:x80000
17 reg = <0x00000000 0x80000000 0 0x80000000>;
23 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
24 <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
27 interrupts = <1 9 0x4>;
32 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
33 <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
34 <1 11 0x8>, /* Virtual PPI, active-low */
35 <1 10 0x8>; /* Hypervisor PPI, active-low */
41 reg = <0x0 0x21c0500 0x0 0x100>;
42 clock-frequency = <0>; /* Updated by bootloader */
43 interrupts = <0 32 0x1>; /* edge triggered */
49 reg = <0x0 0x21c0600 0x0 0x100>;
50 clock-frequency = <0>; /* Updated by bootloader */
51 interrupts = <0 32 0x1>; /* edge triggered */
56 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
57 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
63 #size-cells = <0>;
64 reg = <0x0 0x2100000 0x0 0x10000>;
65 interrupts = <0 26 0x4>; /* Level high type */
72 #size-cells = <0>;
73 reg = <0x0 0x20c0000 0x0 0x10000>,
74 <0x0 0x20000000 0x0 0x10000000>;
81 reg = <0x0 0x3100000 0x0 0x10000>;
82 interrupts = <0 80 0x4>; /* Level high type */
88 reg = <0x0 0x3110000 0x0 0x10000>;
89 interrupts = <0 81 0x4>; /* Level high type */
95 reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
96 0x00 0x03480000 0x0 0x80000 /* lut registers */
97 0x10 0x00000000 0x0 0x20000>; /* configuration space */
103 bus-range = <0x0 0xff>;
104 ranges = <0x81000000 0x0 0x00000000 0x10 0x00020000 0x0 0x00010000 /* downstream I/O */
105 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
110 reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
111 0x00 0x03580000 0x0 0x80000 /* lut registers */
112 0x12 0x00000000 0x0 0x20000>; /* configuration space */
118 bus-range = <0x0 0xff>;
119 ranges = <0x81000000 0x0 0x00000000 0x12 0x00020000 0x0 0x00010000 /* downstream I/O */
120 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
125 reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
126 0x00 0x03680000 0x0 0x80000 /* lut registers */
127 0x14 0x00000000 0x0 0x20000>; /* configuration space */
133 bus-range = <0x0 0xff>;
134 ranges = <0x81000000 0x0 0x00000000 0x14 0x00020000 0x0 0x00010000 /* downstream I/O */
135 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
140 reg = <0x00 0x03700000 0x0 0x80000 /* dbi registers */
141 0x00 0x03780000 0x0 0x80000 /* lut registers */
142 0x16 0x00000000 0x0 0x20000>; /* configuration space */
148 bus-range = <0x0 0xff>;
149 ranges = <0x81000000 0x0 0x00000000 0x16 0x00020000 0x0 0x00010000 /* downstream I/O */
150 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */