arm/dts/fsl-ls1046a.dtsi

2  * Device Tree Include file for Freescale Layerscape-1046A family SoC.
17 	interrupt-parent = <&gic>;
20 		compatible = "fixed-clock";
21 		#clock-cells = <0>;
22 		clock-frequency = <100000000>;
23 		clock-output-names = "sysclk";
26 	gic: interrupt-controller@1400000 {
27 		compatible = "arm,gic-400";
28 		#interrupt-cells = <3>;
29 		interrupt-controller;
38 		compatible = "simple-bus";
39 		#address-cells = <2>;
40 		#size-cells = <2>;
44 			compatible = "fsl,ls1046a-clockgen";
46 			#clock-cells = <2>;
51 			compatible = "fsl,vf610-dspi";
52 			#address-cells = <1>;
53 			#size-cells = <0>;
56 			clock-names = "dspi";
58 			num-cs = <6>;
59 			big-endian;
64 			compatible = "fsl,vf610-dspi";
65 			#address-cells = <1>;
66 			#size-cells = <0>;
69 			clock-names = "dspi";
71 			num-cs = <6>;
72 			big-endian;
77 			compatible = "fsl,ifc", "simple-bus";
82 		i2c0: i2c@2180000 {
83 			compatible = "fsl,vf610-i2c";
84 			#address-cells = <1>;
85 			#size-cells = <0>;
88 			clock-names = "i2c";
93 		i2c1: i2c@2190000 {
94 			compatible = "fsl,vf610-i2c";
95 			#address-cells = <1>;
96 			#size-cells = <0>;
99 			clock-names = "i2c";
104 		i2c2: i2c@21a0000 {
105 			compatible = "fsl,vf610-i2c";
106 			#address-cells = <1>;
107 			#size-cells = <0>;
110 			clock-names = "i2c";
115 		i2c3: i2c@21b0000 {
116 			compatible = "fsl,vf610-i2c";
117 			#address-cells = <1>;
118 			#size-cells = <0>;
121 			clock-names = "i2c";
155 			compatible = "fsl,ls1021a-lpuart";
159 			clock-names = "ipg";
164 			compatible = "fsl,ls1021a-lpuart";
168 			clock-names = "ipg";
173 			compatible = "fsl,ls1021a-lpuart";
177 			clock-names = "ipg";
182 			compatible = "fsl,ls1021a-lpuart";
186 			clock-names = "ipg";
191 			compatible = "fsl,ls1021a-lpuart";
195 			clock-names = "ipg";
200 			compatible = "fsl,ls1021a-lpuart";
204 			clock-names = "ipg";
209 			compatible = "fsl,vf610-qspi";
210 			#address-cells = <1>;
211 			#size-cells = <0>;
214 			reg-names = "QuadSPI", "QuadSPI-memory";
215 			num-cs = <4>;
216 			big-endian;
221 			compatible = "fsl,layerscape-dwc3";
228 			compatible = "fsl,layerscape-dwc3";
235 			compatible = "fsl,layerscape-dwc3";
242 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
247 			reg-names = "dbi", "lut", "ctrl", "config";
248 			big-endian;
249 			#address-cells = <3>;
250 			#size-cells = <2>;
252 			bus-range = <0x0 0xff>;
254 				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
258 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
263 			reg-names = "dbi", "lut", "ctrl", "config";
264 			big-endian;
265 			#address-cells = <3>;
266 			#size-cells = <2>;
268 			num-lanes = <2>;
269 			bus-range = <0x0 0xff>;
271 				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
275 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
280 			reg-names = "dbi", "lut", "ctrl", "config";
281 			big-endian;
282 			#address-cells = <3>;
283 			#size-cells = <2>;
285 			bus-range = <0x0 0xff>;
287 				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */