Lines Matching +full:0 +full:x40000000
21 #clock-cells = <0>;
30 reg = <0x0 0x1410000 0 0x10000>, /* GICD */
31 <0x0 0x1420000 0 0x10000>, /* GICC */
32 <0x0 0x1440000 0 0x20000>, /* GICH */
33 <0x0 0x1460000 0 0x20000>; /* GICV */
34 interrupts = <1 9 0xf08>;
45 reg = <0x0 0x1ee1000 0x0 0x1000>;
53 #size-cells = <0>;
54 reg = <0x0 0x2100000 0x0 0x10000>;
55 interrupts = <0 64 0x4>;
57 clocks = <&clockgen 4 0>;
66 #size-cells = <0>;
67 reg = <0x0 0x2110000 0x0 0x10000>;
68 interrupts = <0 65 0x4>;
70 clocks = <&clockgen 4 0>;
78 reg = <0x0 0x1530000 0x0 0x10000>;
79 interrupts = <0 43 0x4>;
85 #size-cells = <0>;
86 reg = <0x0 0x2180000 0x0 0x10000>;
87 interrupts = <0 56 0x4>;
89 clocks = <&clockgen 4 0>;
96 #size-cells = <0>;
97 reg = <0x0 0x2190000 0x0 0x10000>;
98 interrupts = <0 57 0x4>;
100 clocks = <&clockgen 4 0>;
107 #size-cells = <0>;
108 reg = <0x0 0x21a0000 0x0 0x10000>;
109 interrupts = <0 58 0x4>;
111 clocks = <&clockgen 4 0>;
118 #size-cells = <0>;
119 reg = <0x0 0x21b0000 0x0 0x10000>;
120 interrupts = <0 59 0x4>;
122 clocks = <&clockgen 4 0>;
128 reg = <0x00 0x21c0500 0x0 0x100>;
129 interrupts = <0 54 0x4>;
130 clocks = <&clockgen 4 0>;
135 reg = <0x00 0x21c0600 0x0 0x100>;
136 interrupts = <0 54 0x4>;
137 clocks = <&clockgen 4 0>;
142 reg = <0x0 0x21d0500 0x0 0x100>;
143 interrupts = <0 55 0x4>;
144 clocks = <&clockgen 4 0>;
149 reg = <0x0 0x21d0600 0x0 0x100>;
150 interrupts = <0 55 0x4>;
151 clocks = <&clockgen 4 0>;
156 reg = <0x0 0x2950000 0x0 0x1000>;
157 interrupts = <0 48 0x4>;
158 clocks = <&clockgen 4 0>;
165 reg = <0x0 0x2960000 0x0 0x1000>;
166 interrupts = <0 49 0x4>;
174 reg = <0x0 0x2970000 0x0 0x1000>;
175 interrupts = <0 50 0x4>;
183 reg = <0x0 0x2980000 0x0 0x1000>;
184 interrupts = <0 51 0x4>;
192 reg = <0x0 0x2990000 0x0 0x1000>;
193 interrupts = <0 52 0x4>;
201 reg = <0x0 0x29a0000 0x0 0x1000>;
202 interrupts = <0 53 0x4>;
211 #size-cells = <0>;
212 reg = <0x0 0x1550000 0x0 0x10000>,
213 <0x0 0x40000000 0x0 0x10000000>;
222 reg = <0x0 0x2f00000 0x0 0x10000>;
223 interrupts = <0 60 4>;
229 reg = <0x0 0x3000000 0x0 0x10000>;
230 interrupts = <0 61 4>;
236 reg = <0x0 0x3100000 0x0 0x10000>;
237 interrupts = <0 63 4>;
243 reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
244 0x00 0x03480000 0x0 0x40000 /* lut registers */
245 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
246 0x40 0x00000000 0x0 0x20000>; /* configuration space */
252 bus-range = <0x0 0xff>;
253 ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */
254 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
259 reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
260 0x00 0x03580000 0x0 0x40000 /* lut registers */
261 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
262 0x48 0x00000000 0x0 0x20000>; /* configuration space */
269 bus-range = <0x0 0xff>;
270 ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000 /* downstream I/O */
271 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
276 reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
277 0x00 0x03680000 0x0 0x40000 /* lut registers */
278 0x00 0x036c0000 0x0 0x40000 /* pf controls registers */
279 0x50 0x00000000 0x0 0x20000>; /* configuration space */
285 bus-range = <0x0 0xff>;
286 ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000 /* downstream I/O */
287 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */