Lines Matching +full:spi +full:- +full:cpol
2 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
13 /include/ "fsl-ls1043a.dtsi"
24 bus-num = <0>;
28 #address-cells = <1>;
29 #size-cells = <1>;
30 compatible = "spi-flash";
31 spi-max-frequency = <1000000>; /* input clock */
32 spi-cpol;
33 spi-cpha;
38 #address-cells = <1>;
39 #size-cells = <1>;
40 compatible = "spi-flash";
41 spi-max-frequency = <3500000>;
42 spi-cpol;
43 spi-cpha;
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "spi-flash";
51 spi-max-frequency = <3500000>;
52 spi-cpol;
53 spi-cpha;
59 bus-num = <0>;
63 #address-cells = <1>;
64 #size-cells = <1>;
65 compatible = "spi-flash";
66 spi-max-frequency = <20000000>;
76 #address-cells = <1>;
77 #size-cells = <0>;
80 #address-cells = <1>;
81 #size-cells = <0>;
93 #address-cells = <1>;
94 #size-cells = <0>;
100 shunt-resistor = <1000>;
106 shunt-resistor = <1000>;
111 #address-cells = <1>;
112 #size-cells = <0>;
134 #address-cells = <2>;
135 #size-cells = <1>;
143 #address-cells = <1>;
144 #size-cells = <1>;
145 compatible = "cfi-flash";
147 bank-width = <2>;
148 device-width = <1>;
152 compatible = "fsl,ifc-nand";
153 #address-cells = <1>;
154 #size-cells = <1>;
158 fpga: board-control@2,0 {
159 #address-cells = <1>;
160 #size-cells = <1>;
161 compatible = "simple-bus";
163 bank-width = <1>;
164 device-width = <1>;