Lines Matching +full:vf610 +full:- +full:i2c
4 * SPDX-License-Identifier: GPL-2.0+
11 interrupt-parent = <&gic>;
14 compatible = "fixed-clock";
15 #clock-cells = <0>;
16 clock-frequency = <100000000>;
17 clock-output-names = "sysclk";
20 gic: interrupt-controller@1400000 {
21 compatible = "arm,gic-400";
22 #interrupt-cells = <3>;
23 interrupt-controller;
32 compatible = "simple-bus";
33 #address-cells = <2>;
34 #size-cells = <2>;
38 compatible = "fsl,ls1012a-clockgen";
40 #clock-cells = <2>;
45 compatible = "fsl,vf610-dspi";
46 #address-cells = <1>;
47 #size-cells = <0>;
50 clock-names = "dspi";
52 num-cs = <6>;
53 big-endian;
61 big-endian;
62 bus-width = <4>;
69 big-endian;
70 non-removable;
71 bus-width = <4>;
74 i2c0: i2c@2180000 {
75 compatible = "fsl,vf610-i2c";
76 #address-cells = <1>;
77 #size-cells = <0>;
80 clock-names = "i2c";
85 i2c1: i2c@2190000 {
86 compatible = "fsl,vf610-i2c";
87 #address-cells = <1>;
88 #size-cells = <0>;
91 clock-names = "i2c";
111 compatible = "fsl,vf610-qspi";
112 #address-cells = <1>;
113 #size-cells = <0>;
116 reg-names = "QuadSPI", "QuadSPI-memory";
117 num-cs = <1>;
118 big-endian;
123 compatible = "fsl,ls-pcie", "snps,dw-pcie";
128 reg-names = "dbi", "lut", "ctrl", "config";
129 big-endian;
130 #address-cells = <3>;
131 #size-cells = <2>;
133 bus-range = <0x0 0xff>;
135 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
139 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
143 fsl,usb-erratum-a005697;
147 compatible = "fsl,layerscape-dwc3";