arm/dts/exynos7420.dtsi

7  * SPDX-License-Identifier:	GPL-2.0+
10 /dts-v1/;
12 #include <dt-bindings/clock/exynos7420-clk.h>
17 		compatible = "fixed-clock";
18 		clock-output-names = "fin_pll";
19 		u-boot,dm-pre-reloc;
20 		#clock-cells = <0>;
23 	clock_topc: clock-controller@10570000 {
24 		compatible = "samsung,exynos7-clock-topc";
26 		u-boot,dm-pre-reloc;
27 		#clock-cells = <1>;
28 		clocks = <&fin_pll>;
29 		clock-names = "fin_pll";
32 	clock_top0: clock-controller@105d0000 {
33 		compatible = "samsung,exynos7-clock-top0";
35 		u-boot,dm-pre-reloc;
36 		#clock-cells = <1>;
37 		clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
41 		clock-names = "fin_pll", "dout_sclk_bus0_pll",
46 	clock_peric1: clock-controller@14c80000 {
47 		compatible = "samsung,exynos7-clock-peric1";
49 		u-boot,dm-pre-reloc;
50 		#clock-cells = <1>;
51 		clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
55 		clock-names = "fin_pll", "dout_aclk_peric1_66",
60 		compatible = "samsung,exynos7420-pinctrl";
62 		u-boot,dm-pre-reloc;
64 		serial2_bus: serial2-bus {
65 			samsung,pins = "gpd1-4", "gpd1-5";
66 			samsung,pin-function = <2>;
67 			samsung,pin-pud = <3>;
68 			samsung,pin-drv = <0>;
69 			u-boot,dm-pre-reloc;
74 		compatible = "samsung,exynos4210-uart";
76 		u-boot,dm-pre-reloc;
77 		clocks = <&clock_peric1 PCLK_UART2>,
79 		clock-names = "uart", "clk_uart_baud0";
80 		pinctrl-names = "default";
81 		pinctrl-0 = <&serial2_bus>;