Lines Matching +full:0 +full:x2000
29 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
63 reg = <0x44000000 0x10000>;
71 reg = <0x48180000 0x4000>;
75 #size-cells = <0>;
84 reg = <0x48140000 0x21000>;
88 ranges = <0 0x48140000 0x21000>;
92 reg = <0x800 0x50a>;
94 #size-cells = <0>;
97 pinctrl-single,function-mask = <0xf>;
103 reg = <0x600 0x110>;
106 ranges = <0 0x600 0x110>;
110 reg = <0x20 0x8>;
114 #phy-cells = <0>;
120 reg = <0x28 0x8>;
124 #phy-cells = <0>;
131 #size-cells = <0>;
141 reg = <0x49000000 0x10000>,
142 <0x44e10f90 0x40>;
150 reg = <0x48080000 0x2000>;
158 reg = <0x48032000 0x1000>;
170 reg = <0x4804c000 0x1000>;
181 reg = <0x50000000 0x2000>;
198 reg = <0x48028000 0x1000>;
200 #size-cells = <0>;
209 reg = <0x4802a000 0x1000>;
211 #size-cells = <0>;
221 reg = <0x48200000 0x1000>;
226 reg = <0x480c0000 0x1000>;
233 reg = <0x480c8000 0x2000>;
240 ti,mbox-tx = <3 0 0>;
241 ti,mbox-rx = <0 0 0>;
247 reg = <0x480ca000 0x2000>;
255 #size-cells = <0>;
256 reg = <0x4a100800 0x100>;
259 phy0: ethernet-phy@0 {
270 reg = <0x4a100000 0x800
271 0x4a100900 0x3700>;
274 ti,davinci-ctrl-reg-offset = <0>;
275 ti,davinci-ctrl-mod-reg-offset = <0x900>;
276 ti,davinci-ctrl-ram-offset = <0x2000>;
277 ti,davinci-ctrl-ram-size = <0x2000>;
285 reg = <0x4a120000 0x4000>;
288 ti,davinci-ctrl-reg-offset = <0>;
289 ti,davinci-ctrl-mod-reg-offset = <0x900>;
290 ti,davinci-ctrl-ram-offset = <0x2000>;
291 ti,davinci-ctrl-ram-size = <0x2000>;
298 reg = <0x48030000 0x1000>;
300 #size-cells = <0>;
314 reg = <0x48060000 0x11000>;
323 reg = <0x4802e000 0x2000>;
331 reg = <0x48040000 0x2000>;
338 reg = <0x48042000 0x2000>;
345 reg = <0x48044000 0x2000>;
353 reg = <0x48046000 0x2000>;
361 reg = <0x48048000 0x2000>;
369 reg = <0x4804a000 0x2000>;
378 reg = <0x48020000 0x2000>;
388 reg = <0x48022000 0x2000>;
398 reg = <0x48024000 0x2000>;
408 reg = <0x47401000 0x400000>;
416 reg = <0x47401400 0x400
417 0x47401000 0x200>;
422 interface-type = <0>;
430 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
431 &cppi41dma 2 0 &cppi41dma 3 0
432 &cppi41dma 4 0 &cppi41dma 5 0
433 &cppi41dma 6 0 &cppi41dma 7 0
434 &cppi41dma 8 0 &cppi41dma 9 0
435 &cppi41dma 10 0 &cppi41dma 11 0
436 &cppi41dma 12 0 &cppi41dma 13 0
437 &cppi41dma 14 0 &cppi41dma 0 1
456 reg = <0x47401c00 0x400
457 0x47401800 0x200>;
462 interface-type = <0>;
470 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
471 &cppi41dma 17 0 &cppi41dma 18 0
472 &cppi41dma 19 0 &cppi41dma 20 0
473 &cppi41dma 21 0 &cppi41dma 22 0
474 &cppi41dma 23 0 &cppi41dma 24 0
475 &cppi41dma 25 0 &cppi41dma 26 0
476 &cppi41dma 27 0 &cppi41dma 28 0
477 &cppi41dma 29 0 &cppi41dma 15 1
496 reg = <0x47400000 0x1000
497 0x47402000 0x1000
498 0x47403000 0x1000
499 0x47404000 0x4000>;
512 reg = <0x480c2000 0x1000>;
513 interrupts = <0>;