Lines Matching +full:0 +full:x7ec00000
29 reg = <0x7e003000 0x1000>;
30 interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
40 reg = <0x7e007000 0xf00>;
76 brcm,dma-channel-mask = <0x7f35>;
81 reg = <0x7e00b200 0x200>;
88 reg = <0x7e100000 0x28>;
94 reg = <0x7e101000 0x2000>;
104 reg = <0x7e104000 0x10>;
109 reg = <0x7e00b880 0x40>;
110 interrupts = <0 1>;
111 #mbox-cells = <0>;
116 reg = <0x7e200000 0xb4>;
139 reg = <0x7e201000 0x1000>;
144 arm,primecell-periphid = <0x00241011>;
149 reg = <0x7e203000 0x20>,
150 <0x7e101098 0x02>;
160 reg = <0x7e204000 0x1000>;
164 #size-cells = <0>;
170 reg = <0x7e205000 0x1000>;
174 #size-cells = <0>;
180 reg = <0x7e206000 0x100>;
186 reg = <0x7e207000 0x100>;
190 aux: aux@0x7e215000 {
193 reg = <0x7e215000 0x8>;
199 reg = <0x7e215040 0x40>;
207 reg = <0x7e215080 0x40>;
211 #size-cells = <0>;
217 reg = <0x7e2150c0 0x40>;
221 #size-cells = <0>;
227 reg = <0x7e20c000 0x28>;
237 reg = <0x7e300000 0x100>;
245 reg = <0x7e400000 0x6000>;
251 reg = <0x7e804000 0x1000>;
255 #size-cells = <0>;
261 reg = <0x7e805000 0x1000>;
265 #size-cells = <0>;
271 reg = <0x7e807000 0x100>;
277 reg = <0x7e902000 0x600>,
278 <0x7e808000 0x100>;
289 reg = <0x7e980000 0x10000>;
292 #size-cells = <0>;
297 reg = <0x7ec00000 0x1000>;
309 #size-cells = <0>;
315 #clock-cells = <0>;