Lines Matching +full:0 +full:xf000c000
44 #address-cells = <0>;
45 #size-cells = <0>;
54 reg = <0x20000000 0x10000000>;
60 #clock-cells = <0>;
61 clock-frequency = <0>;
66 #clock-cells = <0>;
67 clock-frequency = <0>;
72 #clock-cells = <0>;
79 reg = <0x00300000 0x8000>;
100 reg = <0xfffff000 0x200>;
106 reg = <0xffffe800 0x200>;
113 reg = <0xfffffc00 0x200>;
117 #size-cells = <0>;
123 #clock-cells = <0>;
131 #clock-cells = <0>;
138 #clock-cells = <0>;
143 plla: pllack@0 {
145 #clock-cells = <0>;
148 reg = <0>;
151 atmel,pll-clk-output-ranges = <745000000 800000000 0 0
152 695000000 750000000 1 0
153 645000000 700000000 2 0
154 595000000 650000000 3 0
155 545000000 600000000 0 1
163 #clock-cells = <0>;
169 #clock-cells = <0>;
176 #clock-cells = <0>;
179 atmel,clk-output-range = <0 133333333>;
188 #clock-cells = <0>;
195 #size-cells = <0>;
199 prog0: prog@0 {
200 #clock-cells = <0>;
201 reg = <0>;
202 interrupts = <AT91_PMC_PCKRDY(0)>;
206 #clock-cells = <0>;
214 #clock-cells = <0>;
221 #size-cells = <0>;
224 #clock-cells = <0>;
230 #clock-cells = <0>;
236 #clock-cells = <0>;
242 #clock-cells = <0>;
248 #clock-cells = <0>;
254 #clock-cells = <0>;
263 #size-cells = <0>;
269 #clock-cells = <0>;
274 #clock-cells = <0>;
279 #clock-cells = <0>;
284 #clock-cells = <0>;
289 #clock-cells = <0>;
294 #clock-cells = <0>;
300 #clock-cells = <0>;
304 #clock-cells = <0>;
309 #clock-cells = <0>;
314 #clock-cells = <0>;
319 #clock-cells = <0>;
324 #clock-cells = <0>;
329 #clock-cells = <0>;
334 #clock-cells = <0>;
339 #clock-cells = <0>;
344 #clock-cells = <0>;
349 #clock-cells = <0>;
354 #clock-cells = <0>;
359 #clock-cells = <0>;
364 #clock-cells = <0>;
369 #clock-cells = <0>;
374 #clock-cells = <0>;
379 #clock-cells = <0>;
387 reg = <0xfffffe00 0x10>;
393 reg = <0xfffffe10 0x10>;
399 reg = <0xfffffe30 0xf>;
406 reg = <0xfffffe50 0x4>;
410 #clock-cells = <0>;
416 #clock-cells = <0>;
423 #clock-cells = <0>;
430 reg = <0xf8008000 0x100>;
431 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
438 reg = <0xf800c000 0x100>;
439 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
446 reg = <0xffffec00 0x200>;
447 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
455 reg = <0xffffee00 0x200>;
456 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
466 ranges = <0xfffff400 0xfffff400 0x800>;
467 reg = <0xfffff400 0x200 /* pioA */
468 0xfffff600 0x200 /* pioB */
469 0xfffff800 0x200 /* pioC */
470 0xfffffa00 0x200 /* pioD */
478 pinctrl_dbgu: dbgu-0 {
486 pinctrl_usart0: usart0-0 {
488 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA0 periph A with pullup */
492 pinctrl_usart0_rts: usart0_rts-0 {
497 pinctrl_usart0_cts: usart0_cts-0 {
502 pinctrl_usart0_sck: usart0_sck-0 {
509 pinctrl_usart1: usart1-0 {
515 pinctrl_usart1_rts: usart1_rts-0 {
520 pinctrl_usart1_cts: usart1_cts-0 {
525 pinctrl_usart1_sck: usart1_sck-0 {
532 pinctrl_usart2: usart2-0 {
538 pinctrl_usart2_rts: usart2_rts-0 {
540 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
543 pinctrl_usart2_cts: usart2_cts-0 {
548 pinctrl_usart2_sck: usart2_sck-0 {
555 pinctrl_uart0: uart0-0 {
563 pinctrl_uart1: uart1-0 {
571 pinctrl_nand: nand-0 {
573 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A Read Enable */
579 AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD6 periph A Data bit 0 */
589 pinctrl_nand_16bits: nand_16bits-0 {
603 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
610 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
619 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
626 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
635 pinctrl_ssc0_tx: ssc0_tx-0 {
642 pinctrl_ssc0_rx: ssc0_rx-0 {
651 pinctrl_spi0: spi0-0 {
660 pinctrl_spi1: spi1-0 {
669 pinctrl_i2c0: i2c0-0 {
677 pinctrl_i2c1: i2c1-0 {
679 <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC0 periph C I2C1 data */
685 pinctrl_i2c2: i2c2-0 {
693 pinctrl_i2c_gpio0: i2c_gpio0-0 {
701 pinctrl_i2c_gpio1: i2c_gpio1-0 {
703 <AT91_PIOC 0 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PC0 gpio multidrive I2C1 data */
709 pinctrl_i2c_gpio2: i2c_gpio2-0 {
717 pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 {
730 pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 {
743 pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 {
752 pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 {
763 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
767 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
771 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
775 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
779 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
783 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
787 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
791 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
795 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
801 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
805 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
809 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
813 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
817 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
821 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
825 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
829 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
833 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
841 reg = <0xfffff400 0x200>;
852 reg = <0xfffff600 0x200>;
864 reg = <0xfffff800 0x200>;
875 reg = <0xfffffa00 0x200>;
887 reg = <0xf0010000 0x4000>;
893 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
901 reg = <0xf0008000 0x600>;
902 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
903 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>;
909 #size-cells = <0>;
915 reg = <0xf000c000 0x600>;
916 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
917 dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>;
923 #size-cells = <0>;
929 reg = <0xfffff200 0x200>;
932 pinctrl-0 = <&pinctrl_dbgu>;
943 reg = <0xf801c000 0x200>;
946 pinctrl-0 = <&pinctrl_usart0>;
957 reg = <0xf8020000 0x200>;
960 pinctrl-0 = <&pinctrl_usart1>;
971 reg = <0xf8024000 0x200>;
974 pinctrl-0 = <&pinctrl_usart2>;
985 reg = <0xf8010000 0x100>;
991 #size-cells = <0>;
993 pinctrl-0 = <&pinctrl_i2c0>;
1000 reg = <0xf8014000 0x100>;
1006 #size-cells = <0>;
1008 pinctrl-0 = <&pinctrl_i2c1>;
1015 reg = <0xf8018000 0x100>;
1021 #size-cells = <0>;
1023 pinctrl-0 = <&pinctrl_i2c2>;
1030 reg = <0xf8040000 0x200>;
1033 pinctrl-0 = <&pinctrl_uart0>;
1041 reg = <0xf8044000 0x200>;
1044 pinctrl-0 = <&pinctrl_uart1>;
1052 #size-cells = <0>;
1054 reg = <0xf804c000 0x100>;
1055 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
1060 atmel,adc-channels-used = <0xffff>;
1070 trigger-value = <0x1>;
1076 trigger-value = <0x2>;
1082 trigger-value = <0x3>;
1088 trigger-value = <0x6>;
1094 #size-cells = <0>;
1096 reg = <0xf0000000 0x100>;
1102 pinctrl-0 = <&pinctrl_spi0>;
1110 #size-cells = <0>;
1112 reg = <0xf0004000 0x100>;
1118 pinctrl-0 = <&pinctrl_spi1>;
1126 #size-cells = <0>;
1128 reg = <0x00500000 0x80000
1129 0xf803c000 0x400>;
1130 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
1135 ep@0 {
1136 reg = <0>;
1190 reg = <0xfffffe40 0x10>;
1201 reg = <0xfffffeb0 0x40>;
1209 reg = <0xf8034000 0x300>;
1221 reg = <0x40000000 0x10000000
1222 0xffffe000 0x600 /* PMECC Registers */
1223 0xffffe600 0x200 /* PMECC Error Location Registers */
1224 0x00108000 0x18000 /* PMECC looup table in ROM code */
1226 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
1231 pinctrl-0 = <&pinctrl_nand>;
1234 0
1241 reg = <0x00600000 0x100000>;
1250 reg = <0x00700000 0x100000>;
1258 i2c-gpio-0 {
1267 #size-cells = <0>;
1269 pinctrl-0 = <&pinctrl_i2c_gpio0>;
1275 gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */
1282 #size-cells = <0>;
1284 pinctrl-0 = <&pinctrl_i2c_gpio1>;
1297 #size-cells = <0>;
1299 pinctrl-0 = <&pinctrl_i2c_gpio2>;