Lines Matching +full:0 +full:x200
44 #address-cells = <0>;
45 #size-cells = <0>;
54 reg = <0x70000000 0x10000000>;
60 #clock-cells = <0>;
61 clock-frequency = <0>;
66 #clock-cells = <0>;
67 clock-frequency = <0>;
72 #clock-cells = <0>;
79 reg = <0x00300000 0x10000>;
100 reg = <0xfffff000 0x200>;
106 reg = <0xffffe400 0x200>;
113 reg = <0xffffe600 0x200>;
120 reg = <0xfffffc00 0x100>;
124 #size-cells = <0>;
130 #clock-cells = <0>;
137 #clock-cells = <0>;
141 plla: pllack@0 {
143 #clock-cells = <0>;
146 reg = <0>;
149 atmel,pll-clk-output-ranges = <745000000 800000000 0 0
150 695000000 750000000 1 0
151 645000000 700000000 2 0
152 595000000 650000000 3 0
153 545000000 600000000 0 1
161 #clock-cells = <0>;
167 #clock-cells = <0>;
174 #clock-cells = <0>;
177 atmel,clk-output-range = <0 133333333>;
184 #clock-cells = <0>;
191 #size-cells = <0>;
195 prog0: prog@0 {
196 #clock-cells = <0>;
197 reg = <0>;
198 interrupts = <AT91_PMC_PCKRDY(0)>;
202 #clock-cells = <0>;
211 #size-cells = <0>;
214 #clock-cells = <0>;
220 #clock-cells = <0>;
226 #clock-cells = <0>;
232 #clock-cells = <0>;
241 #size-cells = <0>;
245 #clock-cells = <0>;
250 #clock-cells = <0>;
255 #clock-cells = <0>;
260 #clock-cells = <0>;
265 #clock-cells = <0>;
270 #clock-cells = <0>;
275 #clock-cells = <0>;
280 #clock-cells = <0>;
285 #clock-cells = <0>;
290 #clock-cells = <0>;
295 #clock-cells = <0>;
300 #clock-cells = <0>;
305 #clock-cells = <0>;
310 #clock-cells = <0>;
315 #clock-cells = <0>;
320 #clock-cells = <0>;
325 #clock-cells = <0>;
330 #clock-cells = <0>;
335 #clock-cells = <0>;
340 #clock-cells = <0>;
345 #clock-cells = <0>;
350 #clock-cells = <0>;
355 #clock-cells = <0>;
360 #clock-cells = <0>;
365 #clock-cells = <0>;
370 #clock-cells = <0>;
375 #clock-cells = <0>;
380 #clock-cells = <0>;
385 #clock-cells = <0>;
393 reg = <0xfffffd00 0x10>;
399 reg = <0xfffffd30 0xf>;
407 reg = <0xfffffd10 0x10>;
413 reg = <0xfff7c000 0x100>;
414 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
421 reg = <0xfffd4000 0x100>;
422 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
429 reg = <0xffffec00 0x200>;
430 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
440 ranges = <0xfffff200 0xfffff200 0xa00>;
441 reg = <0xfffff200 0x200
442 0xfffff400 0x200
443 0xfffff600 0x200
444 0xfffff800 0x200
445 0xfffffa00 0x200
451 0xffffffff 0xffc003ff /* pioA */
452 0xffffffff 0x800f8f00 /* pioB */
453 0xffffffff 0x00000e00 /* pioC */
454 0xffffffff 0xff0c1381 /* pioD */
455 0xffffffff 0x81ffff81 /* pioE */
491 pinctrl_dbgu: dbgu-0 {
499 pinctrl_i2c0: i2c0-0 {
507 pinctrl_i2c1: i2c1-0 {
515 pinctrl_isi_data_0_7: isi-0-data-0-7 {
530 pinctrl_isi_data_8_9: isi-0-data-8-9 {
536 pinctrl_isi_data_10_11: isi-0-data-10-11 {
544 pinctrl_usart0: usart0-0 {
550 pinctrl_usart0_rts: usart0_rts-0 {
555 pinctrl_usart0_cts: usart0_cts-0 {
562 pinctrl_usart1: usart1-0 {
568 pinctrl_usart1_rts: usart1_rts-0 {
573 pinctrl_usart1_cts: usart1_cts-0 {
580 pinctrl_usart2: usart2-0 {
586 pinctrl_usart2_rts: usart2_rts-0 {
591 pinctrl_usart2_cts: usart2_cts-0 {
598 pinctrl_usart3: usart3-0 {
604 pinctrl_usart3_rts: usart3_rts-0 {
609 pinctrl_usart3_cts: usart3_cts-0 {
616 pinctrl_nand: nand-0 {
624 pinctrl_macb_rmii: macb_rmii-0 {
638 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
652 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
654 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A */
659 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
666 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
676 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
683 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
690 pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
700 pinctrl_ssc0_tx: ssc0_tx-0 {
702 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A */
707 pinctrl_ssc0_rx: ssc0_rx-0 {
716 pinctrl_ssc1_tx: ssc1_tx-0 {
723 pinctrl_ssc1_rx: ssc1_rx-0 {
732 pinctrl_spi0: spi0-0 {
734 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI0_MISO pin */
741 pinctrl_spi1: spi1-0 {
750 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
754 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
758 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
762 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
766 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
770 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
774 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
778 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
782 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
788 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
789 atmel,pins = <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
792 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
796 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
800 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
804 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
808 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
812 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
816 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
820 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
826 pinctrl_fb: fb-0 {
828 <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE0 periph A */
864 reg = <0xfffff200 0x200>;
875 reg = <0xfffff400 0x200>;
886 reg = <0xfffff600 0x200>;
897 reg = <0xfffff800 0x200>;
908 reg = <0xfffffa00 0x200>;
919 reg = <0xffffee00 0x200>;
922 pinctrl-0 = <&pinctrl_dbgu>;
930 reg = <0xfff8c000 0x200>;
935 pinctrl-0 = <&pinctrl_usart0>;
943 reg = <0xfff90000 0x200>;
948 pinctrl-0 = <&pinctrl_usart1>;
956 reg = <0xfff94000 0x200>;
961 pinctrl-0 = <&pinctrl_usart2>;
969 reg = <0xfff98000 0x200>;
974 pinctrl-0 = <&pinctrl_usart3>;
982 reg = <0xfffbc000 0x100>;
985 pinctrl-0 = <&pinctrl_macb_rmii>;
993 reg = <0xfffcc000 0x100>;
994 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
1000 reg = <0xfff84000 0x100>;
1003 pinctrl-0 = <&pinctrl_i2c0>;
1005 #size-cells = <0>;
1012 reg = <0xfff88000 0x100>;
1015 pinctrl-0 = <&pinctrl_i2c1>;
1017 #size-cells = <0>;
1024 reg = <0xfff9c000 0x4000>;
1027 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
1035 reg = <0xfffa0000 0x4000>;
1038 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
1046 #size-cells = <0>;
1048 reg = <0xfffb0000 0x100>;
1049 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
1052 atmel,adc-channels-used = <0xff>;
1061 trigger-value = <0x1>;
1066 trigger-value = <0x2>;
1072 trigger-value = <0x3>;
1078 trigger-value = <0x6>;
1084 reg = <0xfffb4000 0x4000>;
1091 #size-cells = <0>;
1097 reg = <0xfffb8000 0x300>;
1106 reg = <0xfff80000 0x600>;
1107 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
1109 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
1112 #size-cells = <0>;
1120 reg = <0xfffd0000 0x600>;
1121 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>;
1126 #size-cells = <0>;
1134 reg = <0xfffffd40 0x10>;
1145 #size-cells = <0>;
1147 reg = <0xfffa4000 0x200>;
1150 pinctrl-0 = <&pinctrl_spi0>;
1158 #size-cells = <0>;
1160 reg = <0xfffa8000 0x200>;
1163 pinctrl-0 = <&pinctrl_spi1>;
1171 #size-cells = <0>;
1173 reg = <0x00600000 0x80000
1174 0xfff78000 0x400>;
1175 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
1180 ep@0 {
1181 reg = <0>;
1235 reg = <0xfffffd50 0x4>;
1239 #clock-cells = <0>;
1246 #clock-cells = <0>;
1254 #clock-cells = <0>;
1261 reg = <0xfffffd20 0x10>;
1269 reg = <0xfffffdb0 0x30>;
1277 reg = <0xfffffd60 0x10>;
1282 fb0: fb@0x00500000 {
1284 reg = <0x00500000 0x1000>;
1287 pinctrl-0 = <&pinctrl_fb>;
1297 reg = <0x40000000 0x10000000
1298 0xffffe200 0x200
1304 pinctrl-0 = <&pinctrl_nand>;
1307 0
1314 reg = <0x00700000 0x100000>;
1323 reg = <0x00800000 0x100000>;
1331 i2c-gpio-0 {
1340 #size-cells = <0>;