Lines Matching +full:0 +full:x200
39 #address-cells = <0>;
40 #size-cells = <0>;
49 reg = <0x20000000 0x08000000>;
55 #clock-cells = <0>;
56 clock-frequency = <0>;
61 #clock-cells = <0>;
62 clock-frequency = <0>;
68 reg = <0x00300000 0x14000>;
73 reg = <0x00500000 0x4000>;
94 reg = <0xfffff000 0x200>;
100 reg = <0xfffffc00 0x100>;
104 #size-cells = <0>;
110 #clock-cells = <0>;
117 #clock-cells = <0>;
121 plla: pllack@0 {
123 #clock-cells = <0>;
126 reg = <0>;
129 atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
135 #clock-cells = <0>;
141 atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
147 #clock-cells = <0>;
150 atmel,clk-output-range = <0 120000000>;
151 atmel,clk-divisors = <1 2 4 0>;
157 #clock-cells = <0>;
158 atmel,clk-divisors = <1 2 4 0>;
165 #size-cells = <0>;
169 prog0: prog@0 {
170 #clock-cells = <0>;
171 reg = <0>;
172 interrupts = <AT91_PMC_PCKRDY(0)>;
176 #clock-cells = <0>;
182 #clock-cells = <0>;
188 #clock-cells = <0>;
197 #size-cells = <0>;
200 #clock-cells = <0>;
206 #clock-cells = <0>;
212 #clock-cells = <0>;
218 #clock-cells = <0>;
224 #clock-cells = <0>;
230 #clock-cells = <0>;
239 #size-cells = <0>;
244 #clock-cells = <0>;
250 #clock-cells = <0>;
256 #clock-cells = <0>;
262 #clock-cells = <0>;
267 #clock-cells = <0>;
272 #clock-cells = <0>;
277 #clock-cells = <0>;
282 #clock-cells = <0>;
287 #clock-cells = <0>;
292 #clock-cells = <0>;
297 #clock-cells = <0>;
302 #clock-cells = <0>;
307 #clock-cells = <0>;
312 #clock-cells = <0>;
317 #clock-cells = <0>;
322 #clock-cells = <0>;
327 #clock-cells = <0>;
332 #clock-cells = <0>;
337 #clock-cells = <0>;
342 #clock-cells = <0>;
347 #clock-cells = <0>;
352 #clock-cells = <0>;
357 #clock-cells = <0>;
362 #clock-cells = <0>;
370 reg = <0xffffe200 0x200>;
375 reg = <0xffffe800 0x200>;
380 reg = <0xfffffd30 0xf>;
387 reg = <0xfff7c000 0x100>;
388 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
395 reg = <0xfffffd00 0x10>;
401 reg = <0xfffffd10 0x10>;
409 ranges = <0xfffff200 0xfffff200 0xa00>;
410 reg = <0xfffff200 0x200
411 0xfffff400 0x200
412 0xfffff600 0x200
413 0xfffff800 0x200
414 0xfffffa00 0x200
419 0xfffffffb 0xffffe07f /* pioA */
420 0x0007ffff 0x39072fff /* pioB */
421 0xffffffff 0x3ffffff8 /* pioC */
422 0xfffffbff 0xffffffff /* pioD */
423 0xffe00fff 0xfbfcff00 /* pioE */
428 pinctrl_dbgu: dbgu-0 {
436 pinctrl_usart0: usart0-0 {
442 pinctrl_usart0_rts: usart0_rts-0 {
447 pinctrl_usart0_cts: usart0_cts-0 {
454 pinctrl_usart1: usart1-0 {
456 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A with pullup */
460 pinctrl_usart1_rts: usart1_rts-0 {
465 pinctrl_usart1_cts: usart1_cts-0 {
472 pinctrl_usart2: usart2-0 {
478 pinctrl_usart2_rts: usart2_rts-0 {
483 pinctrl_usart2_cts: usart2_cts-0 {
490 pinctrl_nand: nand-0 {
498 pinctrl_macb_rmii: macb_rmii-0 {
512 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
526 pinctrl_mmc0_clk: mmc0_clk-0 {
531 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
534 AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA0 periph A with pullup */
537 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
544 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
550 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
559 pinctrl_mmc1_clk: mmc1_clk-0 {
564 pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 {
570 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
577 pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 {
583 pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 {
592 pinctrl_ssc0_tx: ssc0_tx-0 {
594 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB0 periph B */
599 pinctrl_ssc0_rx: ssc0_rx-0 {
608 pinctrl_ssc1_tx: ssc1_tx-0 {
615 pinctrl_ssc1_rx: ssc1_rx-0 {
624 pinctrl_spi0: spi0-0 {
626 <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA0 periph B SPI0_MISO pin */
633 pinctrl_spi1: spi1-0 {
642 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
646 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
650 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
654 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
658 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
662 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
666 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
670 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
674 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
680 pinctrl_fb: fb-0 {
716 pinctrl_ac97: ac97-0 {
718 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A AC97FS pin */
729 reg = <0xfffff200 0x200>;
741 reg = <0xfffff400 0x200>;
753 reg = <0xfffff600 0x200>;
765 reg = <0xfffff800 0x200>;
777 reg = <0xfffffa00 0x200>;
789 reg = <0xffffee00 0x200>;
792 pinctrl-0 = <&pinctrl_dbgu>;
800 reg = <0xfff8c000 0x200>;
805 pinctrl-0 = <&pinctrl_usart0>;
813 reg = <0xfff90000 0x200>;
818 pinctrl-0 = <&pinctrl_usart1>;
826 reg = <0xfff94000 0x200>;
831 pinctrl-0 = <&pinctrl_usart2>;
839 reg = <0xfff98000 0x4000>;
842 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
850 reg = <0xfff9c000 0x4000>;
853 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
861 reg = <0xfffa0000 0x4000>;
864 pinctrl-0 = <&pinctrl_ac97>;
872 reg = <0xfffbc000 0x100>;
875 pinctrl-0 = <&pinctrl_macb_rmii>;
883 reg = <0xfff78000 0x4000>;
892 reg = <0xfff88000 0x100>;
895 #size-cells = <0>;
902 reg = <0xfff80000 0x600>;
903 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
906 #size-cells = <0>;
914 reg = <0xfff84000 0x600>;
915 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
918 #size-cells = <0>;
926 reg = <0xfffffd40 0x10>;
937 #size-cells = <0>;
939 reg = <0xfffa4000 0x200>;
942 pinctrl-0 = <&pinctrl_spi0>;
950 #size-cells = <0>;
952 reg = <0xfffa8000 0x200>;
955 pinctrl-0 = <&pinctrl_spi1>;
963 reg = <0xfffb8000 0x300>;
973 reg = <0xfffac000 0x300>;
976 pinctrl-0 = <&pinctrl_can_rx_tx>;
983 reg = <0xfffffd20 0x10>;
991 reg = <0xfffffd50 0x10>;
999 reg = <0xfffffd60 0x50>;
1004 fb0: fb@0x00700000 {
1006 reg = <0x00700000 0x1000>;
1009 pinctrl-0 = <&pinctrl_fb>;
1019 reg = <0x40000000 0x10000000
1020 0xffffe000 0x200
1025 pinctrl-0 = <&pinctrl_nand>;
1028 0
1035 reg = <0x00a00000 0x100000>;
1043 i2c-gpio-0 {
1052 #size-cells = <0>;