Lines Matching +full:0 +full:xfffdc000
40 #address-cells = <0>;
41 #size-cells = <0>;
50 reg = <0x20000000 0x04000000>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
62 #clock-cells = <0>;
63 clock-frequency = <0>;
68 #clock-cells = <0>;
75 reg = <0x002ff000 0x2000>;
96 reg = <0xfffff000 0x200>;
102 reg = <0xffffea00 0x200>;
107 reg = <0xfffffc00 0x100>;
111 #size-cells = <0>;
117 #clock-cells = <0>;
124 #clock-cells = <0>;
130 #clock-cells = <0>;
137 #clock-cells = <0>;
141 plla: pllack@0 {
143 #clock-cells = <0>;
146 reg = <0>;
149 atmel,pll-clk-output-ranges = <80000000 160000000 0 1>,
155 #clock-cells = <0>;
166 #clock-cells = <0>;
169 atmel,clk-output-range = <0 105000000>;
170 atmel,clk-divisors = <1 2 4 0>;
176 #clock-cells = <0>;
177 atmel,clk-divisors = <1 2 4 0>;
184 #size-cells = <0>;
188 prog0: prog@0 {
189 #clock-cells = <0>;
190 reg = <0>;
191 interrupts = <AT91_PMC_PCKRDY(0)>;
195 #clock-cells = <0>;
204 #size-cells = <0>;
207 #clock-cells = <0>;
213 #clock-cells = <0>;
219 #clock-cells = <0>;
225 #clock-cells = <0>;
234 #size-cells = <0>;
239 #clock-cells = <0>;
245 #clock-cells = <0>;
251 #clock-cells = <0>;
257 #clock-cells = <0>;
262 #clock-cells = <0>;
267 #clock-cells = <0>;
272 #clock-cells = <0>;
277 #clock-cells = <0>;
282 #clock-cells = <0>;
288 #clock-cells = <0>;
292 #clock-cells = <0>;
297 #clock-cells = <0>;
302 #clock-cells = <0>;
307 #clock-cells = <0>;
312 #clock-cells = <0>;
317 #clock-cells = <0>;
322 #clock-cells = <0>;
327 #clock-cells = <0>;
332 #clock-cells = <0>;
337 #clock-cells = <0>;
342 #clock-cells = <0>;
347 #clock-cells = <0>;
352 #clock-cells = <0>;
357 #clock-cells = <0>;
362 #clock-cells = <0>;
370 reg = <0xfffffd00 0x10>;
376 reg = <0xfffffd10 0x10>;
382 reg = <0xfffffd30 0xf>;
389 reg = <0xfffa0000 0x100>;
390 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
391 18 IRQ_TYPE_LEVEL_HIGH 0
392 19 IRQ_TYPE_LEVEL_HIGH 0>;
399 reg = <0xfffdc000 0x100>;
400 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
401 27 IRQ_TYPE_LEVEL_HIGH 0
402 28 IRQ_TYPE_LEVEL_HIGH 0>;
409 reg = <0xfffff400 0x200>;
421 reg = <0xfffff600 0x200>;
433 reg = <0xfffff800 0x200>;
447 ranges = <0xfffff400 0xfffff400 0x600>;
448 reg = <0xfffff400 0x200 /* pioA */
449 0xfffff600 0x200 /* pioB */
450 0xfffff800 0x200 /* pioC */
455 0xffffffff 0xffc00c3b /* pioA */
456 0xffffffff 0x7fff3ccf /* pioB */
457 0xffffffff 0x007fffff /* pioC */
464 pinctrl_dbgu: dbgu-0 {
472 pinctrl_usart0: usart0-0 {
478 pinctrl_usart0_rts: usart0_rts-0 {
483 pinctrl_usart0_cts: usart0_cts-0 {
488 pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
494 pinctrl_usart0_dcd: usart0_dcd-0 {
499 pinctrl_usart0_ri: usart0_ri-0 {
506 pinctrl_usart1: usart1-0 {
512 pinctrl_usart1_rts: usart1_rts-0 {
517 pinctrl_usart1_cts: usart1_cts-0 {
524 pinctrl_usart2: usart2-0 {
530 pinctrl_usart2_rts: usart2_rts-0 {
535 pinctrl_usart2_cts: usart2_cts-0 {
542 pinctrl_usart3: usart3-0 {
548 pinctrl_usart3_rts: usart3_rts-0 {
553 pinctrl_usart3_cts: usart3_cts-0 {
560 pinctrl_uart0: uart0-0 {
568 pinctrl_uart1: uart1-0 {
576 pinctrl_nand: nand-0 {
584 pinctrl_macb_rmii: macb_rmii-0 {
598 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
624 pinctrl_mmc0_clk: mmc0_clk-0 {
629 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
635 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
642 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
645 AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA0 periph B with pullup */
648 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
657 pinctrl_ssc0_tx: ssc0_tx-0 {
664 pinctrl_ssc0_rx: ssc0_rx-0 {
673 pinctrl_spi0: spi0-0 {
675 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */
682 pinctrl_spi1: spi1-0 {
684 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI1_MISO pin */
691 pinctrl_i2c_gpio0: i2c_gpio0-0 {
699 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
703 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
707 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
711 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
715 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
719 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
723 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
727 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
731 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
737 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
741 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
745 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
749 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
750 atmel,pins = <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
753 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
757 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
761 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
765 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
769 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
777 reg = <0xfffff200 0x200>;
780 pinctrl-0 = <&pinctrl_dbgu>;
788 reg = <0xfffb0000 0x200>;
793 pinctrl-0 = <&pinctrl_usart0>;
801 reg = <0xfffb4000 0x200>;
806 pinctrl-0 = <&pinctrl_usart1>;
814 reg = <0xfffb8000 0x200>;
819 pinctrl-0 = <&pinctrl_usart2>;
827 reg = <0xfffd0000 0x200>;
832 pinctrl-0 = <&pinctrl_usart3>;
840 reg = <0xfffd4000 0x200>;
845 pinctrl-0 = <&pinctrl_uart0>;
853 reg = <0xfffd8000 0x200>;
858 pinctrl-0 = <&pinctrl_uart1>;
866 reg = <0xfffc4000 0x100>;
869 pinctrl-0 = <&pinctrl_macb_rmii>;
877 reg = <0xfffa4000 0x4000>;
886 reg = <0xfffac000 0x100>;
889 #size-cells = <0>;
896 reg = <0xfffa8000 0x600>;
897 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
899 #size-cells = <0>;
908 reg = <0xfffbc000 0x4000>;
911 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
919 #size-cells = <0>;
921 reg = <0xfffc8000 0x200>;
924 pinctrl-0 = <&pinctrl_spi0>;
932 #size-cells = <0>;
934 reg = <0xfffcc000 0x200>;
937 pinctrl-0 = <&pinctrl_spi1>;
945 #size-cells = <0>;
947 reg = <0xfffe0000 0x100>;
948 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
952 atmel,adc-channels-used = <0xf>;
959 trigger@0 {
960 reg = <0>;
961 trigger-name = "timer-counter-0";
962 trigger-value = <0x1>;
967 trigger-value = <0x3>;
973 trigger-value = <0x5>;
979 trigger-value = <0xd>;
986 reg = <0xfffffd20 0x10>;
994 reg = <0xfffffd40 0x10>;
1005 reg = <0xfffffd50 0x10>;
1014 reg = <0x40000000 0x10000000
1015 0xffffe800 0x200
1020 pinctrl-0 = <&pinctrl_nand>;
1023 0
1030 reg = <0x00500000 0x100000>;
1038 i2c@0 {
1047 #size-cells = <0>;
1049 pinctrl-0 = <&pinctrl_i2c_gpio0>;