Lines Matching +full:0 +full:x500
70 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
76 reg = <0x1400 0x500>;
81 reg = <0x08000 0x1000>;
82 cache-id-part = <0x100>;
91 pinctrl-0 = <&spi0_pins>;
103 reg = <0x11000 0x100>;
108 reg = <0x11100 0x100>;
113 pinctrl-0 = <&uart2_pins>;
115 reg = <0x12200 0x100>;
119 clocks = <&coreclk 0>;
125 pinctrl-0 = <&uart3_pins>;
127 reg = <0x12300 0x100>;
131 clocks = <&coreclk 0>;
137 reg = <0x18200 0x500>;
142 reg = <0x18220 0x4>;
143 clocks = <&coreclk 0>;
149 reg = <0x18230 0x08>;
155 reg = <0x182b0 0x4
156 0x184d0 0x4>;
163 reg = <0x18700 0x24>, <0x1c054 0x10>;
168 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
185 reg = <0x20800 0x20>;
190 reg = <0x30000 0x4000>;
206 reg = <0x52000 0x500>;
214 reg = <0x60900 0x100
215 0x60b00 0x100>;
242 reg = <0xF0900 0x100
243 0xF0B00 0x100>;
266 #clock-cells = <0>;