Lines Matching +full:3 +full:- +full:port
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is dual-licensed: you can use it either under the terms
50 #include "armada-xp.dtsi"
54 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
64 #address-cells = <1>;
65 #size-cells = <0>;
66 enable-method = "marvell,armada-xp-smp";
70 compatible = "marvell,sheeva-v7";
73 clock-latency = <1000000>;
78 compatible = "marvell,sheeva-v7";
81 clock-latency = <1000000>;
86 compatible = "marvell,sheeva-v7";
89 clock-latency = <1000000>;
92 cpu@3 {
94 compatible = "marvell,sheeva-v7";
95 reg = <3>;
96 clocks = <&cpuclk 3>;
97 clock-latency = <1000000>;
107 pcie-controller {
108 compatible = "marvell,armada-xp-pcie";
112 #address-cells = <3>;
113 #size-cells = <2>;
115 msi-parent = <&mpic>;
116 bus-range = <0x00 0xff>;
119 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
120 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
121 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
122 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
123 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
124 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
125 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
126 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
127 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
128 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
129 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
130 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
131 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
132 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
133 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
134 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
135 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
136 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
138 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
139 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
140 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
141 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
142 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
143 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
144 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
145 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
147 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
148 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
150 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
151 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
155 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
157 #address-cells = <3>;
158 #size-cells = <2>;
159 #interrupt-cells = <1>;
162 interrupt-map-mask = <0 0 0 0>;
163 interrupt-map = <0 0 0 0 &mpic 58>;
164 marvell,pcie-port = <0>;
165 marvell,pcie-lane = <0>;
172 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
174 #address-cells = <3>;
175 #size-cells = <2>;
176 #interrupt-cells = <1>;
179 interrupt-map-mask = <0 0 0 0>;
180 interrupt-map = <0 0 0 0 &mpic 59>;
181 marvell,pcie-port = <0>;
182 marvell,pcie-lane = <1>;
187 pcie@3,0 {
189 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
191 #address-cells = <3>;
192 #size-cells = <2>;
193 #interrupt-cells = <1>;
196 interrupt-map-mask = <0 0 0 0>;
197 interrupt-map = <0 0 0 0 &mpic 60>;
198 marvell,pcie-port = <0>;
199 marvell,pcie-lane = <2>;
206 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
208 #address-cells = <3>;
209 #size-cells = <2>;
210 #interrupt-cells = <1>;
213 interrupt-map-mask = <0 0 0 0>;
214 interrupt-map = <0 0 0 0 &mpic 61>;
215 marvell,pcie-port = <0>;
216 marvell,pcie-lane = <3>;
223 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
225 #address-cells = <3>;
226 #size-cells = <2>;
227 #interrupt-cells = <1>;
230 interrupt-map-mask = <0 0 0 0>;
231 interrupt-map = <0 0 0 0 &mpic 62>;
232 marvell,pcie-port = <1>;
233 marvell,pcie-lane = <0>;
240 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
242 #address-cells = <3>;
243 #size-cells = <2>;
244 #interrupt-cells = <1>;
247 interrupt-map-mask = <0 0 0 0>;
248 interrupt-map = <0 0 0 0 &mpic 63>;
249 marvell,pcie-port = <1>;
250 marvell,pcie-lane = <1>;
257 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
259 #address-cells = <3>;
260 #size-cells = <2>;
261 #interrupt-cells = <1>;
264 interrupt-map-mask = <0 0 0 0>;
265 interrupt-map = <0 0 0 0 &mpic 64>;
266 marvell,pcie-port = <1>;
267 marvell,pcie-lane = <2>;
274 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
276 #address-cells = <3>;
277 #size-cells = <2>;
278 #interrupt-cells = <1>;
281 interrupt-map-mask = <0 0 0 0>;
282 interrupt-map = <0 0 0 0 &mpic 65>;
283 marvell,pcie-port = <1>;
284 marvell,pcie-lane = <3>;
291 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
293 #address-cells = <3>;
294 #size-cells = <2>;
295 #interrupt-cells = <1>;
298 interrupt-map-mask = <0 0 0 0>;
299 interrupt-map = <0 0 0 0 &mpic 99>;
300 marvell,pcie-port = <2>;
301 marvell,pcie-lane = <0>;
308 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
310 #address-cells = <3>;
311 #size-cells = <2>;
312 #interrupt-cells = <1>;
315 interrupt-map-mask = <0 0 0 0>;
316 interrupt-map = <0 0 0 0 &mpic 103>;
317 marvell,pcie-port = <3>;
318 marvell,pcie-lane = <0>;
324 internal-regs {
326 compatible = "marvell,orion-gpio";
329 gpio-controller;
330 #gpio-cells = <2>;
331 interrupt-controller;
332 #interrupt-cells = <2>;
337 compatible = "marvell,orion-gpio";
340 gpio-controller;
341 #gpio-cells = <2>;
342 interrupt-controller;
343 #interrupt-cells = <2>;
348 compatible = "marvell,orion-gpio";
350 ngpios = <3>;
351 gpio-controller;
352 #gpio-cells = <2>;
353 interrupt-controller;
354 #interrupt-cells = <2>;
359 compatible = "marvell,armada-xp-neta";
370 compatible = "marvell,mv78460-pinctrl";