Lines Matching +full:0 +full:x81000000
65 #size-cells = <0>;
68 cpu@0 {
71 reg = <0>;
72 clocks = <&cpuclk 0>;
103 * MV78460 has 4 PCIe units Gen2.0: Two units can be
116 bus-range = <0x00 0xff>;
119 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
120 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
121 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
122 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
123 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
124 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
125 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
126 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
127 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
128 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
129 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
130 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
131 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
132 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
133 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
134 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
135 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
136 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
138 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
139 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
140 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
141 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
142 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
143 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
144 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
145 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
147 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
148 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
150 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
151 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
153 pcie@1,0 {
155 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
156 reg = <0x0800 0 0 0 0>;
160 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
161 0x81000000 0 0 0x81000000 0x1 0 1 0>;
162 interrupt-map-mask = <0 0 0 0>;
163 interrupt-map = <0 0 0 0 &mpic 58>;
164 marvell,pcie-port = <0>;
165 marvell,pcie-lane = <0>;
170 pcie@2,0 {
172 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
173 reg = <0x1000 0 0 0 0>;
177 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
178 0x81000000 0 0 0x81000000 0x2 0 1 0>;
179 interrupt-map-mask = <0 0 0 0>;
180 interrupt-map = <0 0 0 0 &mpic 59>;
181 marvell,pcie-port = <0>;
187 pcie@3,0 {
189 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
190 reg = <0x1800 0 0 0 0>;
194 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
195 0x81000000 0 0 0x81000000 0x3 0 1 0>;
196 interrupt-map-mask = <0 0 0 0>;
197 interrupt-map = <0 0 0 0 &mpic 60>;
198 marvell,pcie-port = <0>;
204 pcie@4,0 {
206 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
207 reg = <0x2000 0 0 0 0>;
211 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
212 0x81000000 0 0 0x81000000 0x4 0 1 0>;
213 interrupt-map-mask = <0 0 0 0>;
214 interrupt-map = <0 0 0 0 &mpic 61>;
215 marvell,pcie-port = <0>;
221 pcie@5,0 {
223 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
224 reg = <0x2800 0 0 0 0>;
228 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
229 0x81000000 0 0 0x81000000 0x5 0 1 0>;
230 interrupt-map-mask = <0 0 0 0>;
231 interrupt-map = <0 0 0 0 &mpic 62>;
233 marvell,pcie-lane = <0>;
238 pcie@6,0 {
240 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
241 reg = <0x3000 0 0 0 0>;
245 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
246 0x81000000 0 0 0x81000000 0x6 0 1 0>;
247 interrupt-map-mask = <0 0 0 0>;
248 interrupt-map = <0 0 0 0 &mpic 63>;
255 pcie@7,0 {
257 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
258 reg = <0x3800 0 0 0 0>;
262 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
263 0x81000000 0 0 0x81000000 0x7 0 1 0>;
264 interrupt-map-mask = <0 0 0 0>;
265 interrupt-map = <0 0 0 0 &mpic 64>;
272 pcie@8,0 {
274 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
275 reg = <0x4000 0 0 0 0>;
279 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
280 0x81000000 0 0 0x81000000 0x8 0 1 0>;
281 interrupt-map-mask = <0 0 0 0>;
282 interrupt-map = <0 0 0 0 &mpic 65>;
289 pcie@9,0 {
291 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
292 reg = <0x4800 0 0 0 0>;
296 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
297 0x81000000 0 0 0x81000000 0x9 0 1 0>;
298 interrupt-map-mask = <0 0 0 0>;
299 interrupt-map = <0 0 0 0 &mpic 99>;
301 marvell,pcie-lane = <0>;
306 pcie@10,0 {
308 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
309 reg = <0x5000 0 0 0 0>;
313 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
314 0x81000000 0 0 0x81000000 0xa 0 1 0>;
315 interrupt-map-mask = <0 0 0 0>;
316 interrupt-map = <0 0 0 0 &mpic 103>;
318 marvell,pcie-lane = <0>;
327 reg = <0x18100 0x40>;
338 reg = <0x18140 0x40>;
349 reg = <0x18180 0x40>;
360 reg = <0x34000 0x4000>;