Lines Matching +full:0 +full:x81000000
64 #size-cells = <0>;
67 cpu@0 {
70 reg = <0>;
71 clocks = <&cpuclk 0>;
86 * MV78260 has 3 PCIe units Gen2.0: Two units can be
99 bus-range = <0x00 0xff>;
102 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
103 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
104 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
105 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
106 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
107 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
108 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
109 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
110 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
111 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
112 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
113 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
114 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
115 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
116 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
117 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
118 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
120 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
121 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
122 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
123 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
124 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
125 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
126 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
127 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
129 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
130 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
132 pcie@1,0 {
134 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
135 reg = <0x0800 0 0 0 0>;
139 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
140 0x81000000 0 0 0x81000000 0x1 0 1 0>;
141 interrupt-map-mask = <0 0 0 0>;
142 interrupt-map = <0 0 0 0 &mpic 58>;
143 marvell,pcie-port = <0>;
144 marvell,pcie-lane = <0>;
149 pcie@2,0 {
151 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
152 reg = <0x1000 0 0 0 0>;
156 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
157 0x81000000 0 0 0x81000000 0x2 0 1 0>;
158 interrupt-map-mask = <0 0 0 0>;
159 interrupt-map = <0 0 0 0 &mpic 59>;
160 marvell,pcie-port = <0>;
166 pcie@3,0 {
168 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
169 reg = <0x1800 0 0 0 0>;
173 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
174 0x81000000 0 0 0x81000000 0x3 0 1 0>;
175 interrupt-map-mask = <0 0 0 0>;
176 interrupt-map = <0 0 0 0 &mpic 60>;
177 marvell,pcie-port = <0>;
183 pcie@4,0 {
185 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
186 reg = <0x2000 0 0 0 0>;
190 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
191 0x81000000 0 0 0x81000000 0x4 0 1 0>;
192 interrupt-map-mask = <0 0 0 0>;
193 interrupt-map = <0 0 0 0 &mpic 61>;
194 marvell,pcie-port = <0>;
200 pcie@5,0 {
202 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
203 reg = <0x2800 0 0 0 0>;
207 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
208 0x81000000 0 0 0x81000000 0x5 0 1 0>;
209 interrupt-map-mask = <0 0 0 0>;
210 interrupt-map = <0 0 0 0 &mpic 62>;
212 marvell,pcie-lane = <0>;
217 pcie@6,0 {
219 assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
220 reg = <0x3000 0 0 0 0>;
224 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
225 0x81000000 0 0 0x81000000 0x6 0 1 0>;
226 interrupt-map-mask = <0 0 0 0>;
227 interrupt-map = <0 0 0 0 &mpic 63>;
234 pcie@7,0 {
236 assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
237 reg = <0x3800 0 0 0 0>;
241 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
242 0x81000000 0 0 0x81000000 0x7 0 1 0>;
243 interrupt-map-mask = <0 0 0 0>;
244 interrupt-map = <0 0 0 0 &mpic 64>;
251 pcie@8,0 {
253 assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
254 reg = <0x4000 0 0 0 0>;
258 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
259 0x81000000 0 0 0x81000000 0x8 0 1 0>;
260 interrupt-map-mask = <0 0 0 0>;
261 interrupt-map = <0 0 0 0 &mpic 65>;
268 pcie@9,0 {
270 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
271 reg = <0x4800 0 0 0 0>;
275 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
276 0x81000000 0 0 0x81000000 0x9 0 1 0>;
277 interrupt-map-mask = <0 0 0 0>;
278 interrupt-map = <0 0 0 0 &mpic 99>;
280 marvell,pcie-lane = <0>;
289 reg = <0x18100 0x40>;
300 reg = <0x18140 0x40>;
311 reg = <0x18180 0x40>;
322 reg = <0x34000 0x4000>;