Lines Matching +full:interrupts +full:- +full:extended
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * This file is dual-licensed: you can use it either under the terms
50 #include <dt-bindings/interrupt-controller/arm-gic.h>
51 #include <dt-bindings/interrupt-controller/irq.h>
67 compatible = "arm,cortex-a9-pmu";
68 interrupts-extended = <&mpic 3>;
72 compatible = "marvell,armada380-mbus", "simple-bus";
73 u-boot,dm-pre-reloc;
74 #address-cells = <2>;
75 #size-cells = <1>;
77 interrupt-parent = <&gic>;
78 pcie-mem-aperture = <0xe0000000 0x8000000>;
79 pcie-io-aperture = <0xe8000000 0x100000>;
86 devbus-bootcs {
87 compatible = "marvell,mvebu-devbus";
90 #address-cells = <1>;
91 #size-cells = <1>;
96 devbus-cs0 {
97 compatible = "marvell,mvebu-devbus";
100 #address-cells = <1>;
101 #size-cells = <1>;
106 devbus-cs1 {
107 compatible = "marvell,mvebu-devbus";
110 #address-cells = <1>;
111 #size-cells = <1>;
116 devbus-cs2 {
117 compatible = "marvell,mvebu-devbus";
120 #address-cells = <1>;
121 #size-cells = <1>;
126 devbus-cs3 {
127 compatible = "marvell,mvebu-devbus";
130 #address-cells = <1>;
131 #size-cells = <1>;
136 internal-regs {
137 compatible = "simple-bus";
138 u-boot,dm-pre-reloc;
139 #address-cells = <1>;
140 #size-cells = <1>;
143 L2: cache-controller@8000 {
144 compatible = "arm,pl310-cache";
146 cache-unified;
147 cache-level = <2>;
151 compatible = "arm,cortex-a9-scu";
156 compatible = "arm,cortex-a9-twd-timer";
158 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
162 gic: interrupt-controller@d000 {
163 compatible = "arm,cortex-a9-gic";
164 #interrupt-cells = <3>;
165 #size-cells = <0>;
166 interrupt-controller;
172 compatible = "marvell,armada-380-spi",
173 "marvell,orion-spi";
175 #address-cells = <1>;
176 #size-cells = <0>;
177 cell-index = <0>;
178 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
184 compatible = "marvell,armada-380-spi",
185 "marvell,orion-spi";
187 #address-cells = <1>;
188 #size-cells = <0>;
189 cell-index = <1>;
190 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
196 compatible = "marvell,mv64xxx-i2c";
198 #address-cells = <1>;
199 #size-cells = <0>;
200 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
201 timeout-ms = <1000>;
207 compatible = "marvell,mv64xxx-i2c";
209 #address-cells = <1>;
210 #size-cells = <0>;
211 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
212 timeout-ms = <1000>;
218 compatible = "snps,dw-apb-uart";
220 reg-shift = <2>;
221 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
222 reg-io-width = <1>;
228 compatible = "snps,dw-apb-uart";
230 reg-shift = <2>;
231 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
232 reg-io-width = <1>;
240 ge0_rgmii_pins: ge-rgmii-pins-0 {
248 ge1_rgmii_pins: ge-rgmii-pins-1 {
256 i2c0_pins: i2c-pins-0 {
261 mdio_pins: mdio-pins {
266 ref_clk0_pins: ref-clk-pins-0 {
271 ref_clk1_pins: ref-clk-pins-1 {
276 spi0_pins: spi-pins-0 {
282 spi1_pins: spi-pins-1 {
288 uart0_pins: uart-pins-0 {
293 uart1_pins: uart-pins-1 {
298 sdhci_pins: sdhci-pins {
306 sata0_pins: sata-pins-0 {
311 sata1_pins: sata-pins-1 {
316 sata2_pins: sata-pins-2 {
321 sata3_pins: sata-pins-3 {
328 compatible = "marvell,orion-gpio";
331 gpio-controller;
332 #gpio-cells = <2>;
333 interrupt-controller;
334 #interrupt-cells = <2>;
335 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
342 compatible = "marvell,orion-gpio";
345 gpio-controller;
346 #gpio-cells = <2>;
347 interrupt-controller;
348 #interrupt-cells = <2>;
349 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
355 system-controller@18200 {
356 compatible = "marvell,armada-380-system-controller",
357 "marvell,armada-370-xp-system-controller";
361 gateclk: clock-gating-control@18220 {
362 compatible = "marvell,armada-380-gating-clock";
365 #clock-cells = <1>;
368 coreclk: mvebu-sar@18600 {
369 compatible = "marvell,armada-380-core-clock";
371 #clock-cells = <1>;
374 mbusc: mbus-controller@20000 {
375 compatible = "marvell,mbus-controller";
379 mpic: interrupt-controller@20a00 {
382 #interrupt-cells = <1>;
383 #size-cells = <1>;
384 interrupt-controller;
385 msi-controller;
386 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
390 compatible = "marvell,armada-380-timer",
391 "marvell,armada-xp-timer";
393 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
400 clock-names = "nbclk", "fixed";
404 compatible = "marvell,armada-380-wdt";
407 clock-names = "nbclk", "fixed";
411 compatible = "marvell,armada-370-cpu-reset";
415 mpcore-soc-ctrl@20d20 {
416 compatible = "marvell,armada-380-mpcore-soc-ctrl";
420 coherency-fabric@21010 {
421 compatible = "marvell,armada-380-coherency-fabric";
426 compatible = "marvell,armada-380-pmsu";
431 compatible = "marvell,armada-370-neta";
433 interrupts-extended = <&mpic 10>;
439 compatible = "marvell,armada-370-neta";
441 interrupts-extended = <&mpic 12>;
447 compatible = "marvell,orion-ehci";
449 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
455 compatible = "marvell,orion-xor";
462 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
467 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
475 compatible = "marvell,orion-xor";
482 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
487 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
495 compatible = "marvell,armada-370-neta";
497 interrupts-extended = <&mpic 8>;
503 #address-cells = <1>;
504 #size-cells = <0>;
505 compatible = "marvell,orion-mdio";
511 compatible = "marvell,armada-380-rtc";
513 reg-names = "rtc", "rtc-soc";
514 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
518 compatible = "marvell,armada-380-ahci";
520 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
526 compatible = "marvell,armada-380-ahci";
528 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
534 compatible = "marvell,armada-380-corediv-clock";
536 #clock-cells = <1>;
538 clock-output-names = "nand";
542 compatible = "marvell,armada380-thermal";
548 compatible = "marvell,armada370-nand";
550 #address-cells = <1>;
551 #size-cells = <1>;
552 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
558 compatible = "marvell,armada-380-sdhci";
559 reg-names = "sdhci", "mbus", "conf-sdio3";
563 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
565 mrvl,clk-delay-cycles = <0x1F>;
570 compatible = "marvell,armada-380-xhci";
572 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
578 compatible = "marvell,armada-380-xhci";
580 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
590 compatible = "fixed-clock";
591 #clock-cells = <0>;
592 clock-frequency = <1000000000>;
597 compatible = "fixed-clock";
598 #clock-cells = <0>;
599 clock-frequency = <25000000>;