Lines Matching +full:0 +full:xdc000
78 pcie-mem-aperture = <0xe0000000 0x8000000>;
79 pcie-io-aperture = <0xe8000000 0x100000>;
83 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
88 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
89 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
92 clocks = <&coreclk 0>;
98 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
99 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
102 clocks = <&coreclk 0>;
108 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
109 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
112 clocks = <&coreclk 0>;
118 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
119 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
122 clocks = <&coreclk 0>;
128 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
129 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
132 clocks = <&coreclk 0>;
141 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
145 reg = <0x8000 0x1000>;
152 reg = <0xc000 0x58>;
157 reg = <0xc600 0x20>;
165 #size-cells = <0>;
167 reg = <0xd000 0x1000>,
168 <0xc100 0x100>;
174 reg = <0x10600 0x50>;
176 #size-cells = <0>;
177 cell-index = <0>;
179 clocks = <&coreclk 0>;
186 reg = <0x10680 0x50>;
188 #size-cells = <0>;
191 clocks = <&coreclk 0>;
197 reg = <0x11000 0x20>;
199 #size-cells = <0>;
202 clocks = <&coreclk 0>;
208 reg = <0x11100 0x20>;
210 #size-cells = <0>;
213 clocks = <&coreclk 0>;
219 reg = <0x12000 0x100>;
223 clocks = <&coreclk 0>;
229 reg = <0x12100 0x100>;
233 clocks = <&coreclk 0>;
238 reg = <0x18000 0x20>;
240 ge0_rgmii_pins: ge-rgmii-pins-0 {
256 i2c0_pins: i2c-pins-0 {
266 ref_clk0_pins: ref-clk-pins-0 {
276 spi0_pins: spi-pins-0 {
288 uart0_pins: uart-pins-0 {
306 sata0_pins: sata-pins-0 {
329 reg = <0x18100 0x40>;
343 reg = <0x18140 0x40>;
358 reg = <0x18200 0x100>;
363 reg = <0x18220 0x4>;
364 clocks = <&coreclk 0>;
370 reg = <0x18600 0x04>;
376 reg = <0x20000 0x100>, <0x20180 0x20>;
381 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
392 reg = <0x20300 0x30>, <0x21040 0x30>;
405 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
412 reg = <0x20800 0x10>;
417 reg = <0x20d20 0x6c>;
422 reg = <0x21010 0x1c>;
427 reg = <0x22000 0x1000>;
432 reg = <0x30000 0x4000>;
440 reg = <0x34000 0x4000>;
448 reg = <0x58000 0x500>;
456 reg = <0x60800 0x100
457 0x60a00 0x100>;
476 reg = <0x60900 0x100
477 0x60b00 0x100>;
496 reg = <0x70000 0x4000>;
504 #size-cells = <0>;
506 reg = <0x72004 0x4>;
512 reg = <0xa3800 0x20>, <0x184a0 0x0c>;
519 reg = <0xa8000 0x2000>;
527 reg = <0xe0000 0x2000>;
535 reg = <0xe4250 0xc>;
543 reg = <0xe4078 0x4>, <0xe4074 0x4>;
549 reg = <0xd0000 0x54>;
553 clocks = <&coredivclk 0>;
560 reg = <0xd8000 0x1000>,
561 <0xdc000 0x100>,
562 <0x18454 0x4>;
565 mrvl,clk-delay-cycles = <0x1F>;
571 reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
579 reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
591 #clock-cells = <0>;
598 #clock-cells = <0>;