arm/dts/armada-385.dtsi

57 		#size-cells = <0>;
60 		cpu@0 {
63 			reg = <0>;
88 			bus-range = <0x00 0xff>;
91 			       <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
92 				0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
93 				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
94 				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
95 				0x82000000 0x1 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
96 				0x81000000 0x1 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO  */
97 				0x82000000 0x2 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
98 				0x81000000 0x2 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO  */
99 				0x82000000 0x3 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
100 				0x81000000 0x3 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO  */
101 				0x82000000 0x4 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
102 				0x81000000 0x4 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO  */>;
107 			 * pcie@4,0 is not available.
109 			pcie@1,0 {
111 				assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
112 				reg = <0x0800 0 0 0 0>;
116 				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
117 					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
118 				interrupt-map-mask = <0 0 0 0>;
119 				interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
120 				marvell,pcie-port = <0>;
121 				marvell,pcie-lane = <0>;
127 			pcie@2,0 {
129 				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
130 				reg = <0x1000 0 0 0 0>;
134 				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
135 					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
136 				interrupt-map-mask = <0 0 0 0>;
137 				interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
139 				marvell,pcie-lane = <0>;
145 			pcie@3,0 {
147 				assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
148 				reg = <0x1800 0 0 0 0>;
152 				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
153 					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
154 				interrupt-map-mask = <0 0 0 0>;
155 				interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
157 				marvell,pcie-lane = <0>;
163 			 * x1 port only available when pcie@1,0 is
166 			pcie@4,0 {
168 				assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
169 				reg = <0x2000 0 0 0 0>;
173 				ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
174 					  0x81000000 0 0 0x81000000 0x4 0 1 0>;
175 				interrupt-map-mask = <0 0 0 0>;
176 				interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
178 				marvell,pcie-lane = <0>;